[PATCH] D36663: [X86][Haswell] Updating HSW instruction scheduling information

[Gadi Haber via Phabricator via llvm-commits]

gadi.haber added inline comments.


================
Comment at: lib/Target/X86/X86SchedHaswell.td:2372
+def: InstRW<[HWWriteResGroup34], (instregex "BEXTR64rr")>;
+def: InstRW<[HWWriteResGroup34], (instregex "BSWAP(16|32|64)r")>;
+
----------------
craig.topper wrote:
> BSWAP16r seems to no longer be present.
Yes. Removed it temporarily for performance evaluation.
Brought it back.


================
Comment at: lib/Target/X86/X86SchedHaswell.td:3195
+}
+def: InstRW<[HWWriteResGroup74_32], (instregex "IMUL32r")>;
+def: InstRW<[HWWriteResGroup74_32], (instregex "MUL32r")>;
----------------
craig.topper wrote:
> Is MUL32r/IMUL32r really different than MULX32rr?
yes. This one is different.


Repository:
  rL LLVM

https://reviews.llvm.org/D36663