[PATCH] D36663: [X86][Haswell] Updating HSW instruction scheduling information
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 24 15:30:31 PDT 2017
craig.topper added inline comments.
================
Comment at: lib/Target/X86/X86SchedHaswell.td:2372
+def: InstRW<[HWWriteResGroup34], (instregex "BEXTR64rr")>;
+def: InstRW<[HWWriteResGroup34], (instregex "BSWAP(16|32|64)r")>;
+
----------------
BSWAP16r seems to no longer be present.
================
Comment at: lib/Target/X86/X86SchedHaswell.td:3195
+}
+def: InstRW<[HWWriteResGroup74_32], (instregex "IMUL32r")>;
+def: InstRW<[HWWriteResGroup74_32], (instregex "MUL32r")>;
----------------
Is MUL32r/IMUL32r really different than MULX32rr?
Repository:
rL LLVM
https://reviews.llvm.org/D36663
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