[PATCH] D37102: [AArch64] Add FMOVH0: materialize 0 using zero register for f16 values

[Sjoerd Meijer via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL311662: [AArch64] Add FMOVH0: materialize 0 using zero register for f16 values (authored by SjoerdMeijer).

Changed prior to commit:
  https://reviews.llvm.org/D37102?vs=112536&id=112562#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D37102

Files:
  llvm/trunk/lib/Target/AArch64/AArch64AsmPrinter.cpp
  llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp
  llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/trunk/test/CodeGen/AArch64/f16-imm.ll

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