[PATCH] D37088: [x86] NFC: More refactoring to pave the way to extending this ISel logic to handle other x86 pseudos that carry flags and thus can't be matched by our ISel patterns with fused memory accesses.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

Is your first version going to handle just registers or immediates too/



================
Comment at: lib/Target/X86/X86ISelDAGToDAG.cpp:1959
+  case X86ISD::DEC:
+    return SelectSize({{MVT::i64, X86::DEC64m},
+                       {MVT::i32, X86::DEC32m},
----------------
Any real reason to pass the load sizes with this? Could we just define an order and just map the types to an index without a loop. Feels like the types starting getting repetitive if we extend this to ADD/SUB/AND/OR/XOR/ADC/SBB which all have this problem.


https://reviews.llvm.org/D37088