[PATCH] D36788: The issues with X86 prefixes

[Andrew V. Tischenko via Phabricator via llvm-commits]

avt77 added inline comments.


================
Comment at: lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp:295
 {
+  if (insn->mode == MODE_64BIT) {
+    uint8_t nextByte;
----------------
craig.topper wrote:
> What about 32-bit mode?
I was sure that SSE2, etc. work on 64-bit CPUs only but it seems I was wrong: Wikipedia says:

The following IA-32 CPUs support SSE2:
Intel NetBurst-based CPUs (Pentium 4, Xeon, Celeron, Pentium D, Celeron D)
Intel Pentium M and Celeron M
Intel Atom
Transmeta Efficeon
VIA C7

OK, I'll fix it.


https://reviews.llvm.org/D36788