[PATCH] D36663: [X86][Haswell] Updating HSW instruction scheduling information

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: lib/Target/X86/X86SchedHaswell.td:2722
+def HWWriteResGroup52 : SchedWriteRes<[HWPort1,HWPort23]> {
+  let Latency = 3;
+  let NumMicroOps = 2;
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gadi.haber wrote:
> craig.topper wrote:
> > gadi.haber wrote:
> > > craig.topper wrote:
> > > > Should this account for load latency?
> > > yes, according to the SNB architects.
> > If it shoudl include load latency shouldn't it have a latency of more than 3? ADDPDrr is in a group with latency 3. So shoudln't ADDPrm be more than 3?
> The scheduling model is based on the fact that there are no memory latencies effects, i.e., no cache misses and everything is in the 1st level cache.
> This is the model successfully used and constantly verified by the architects.
> The performance measurements we ran support this model.
> 
I understand assuming everyting is in L1.

But in the SandyBridge model you have ADDPDrr as 3 cycles and ADDPDrm as 9 cycles. So it seems you're accounting for the load as being 6 cycles. But in Haswell you have both as 3 cycles. So loads from the L1 are free on Haswell?



Repository:
  rL LLVM

https://reviews.llvm.org/D36663