[PATCH] D36663: [X86][Haswell] Updating HSW instruction scheduling information

[Gadi Haber via Phabricator via llvm-commits]

gadi.haber added inline comments.


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Comment at: lib/Target/X86/X86SchedHaswell.td:2722
+def HWWriteResGroup52 : SchedWriteRes<[HWPort1,HWPort23]> {
+  let Latency = 3;
+  let NumMicroOps = 2;
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craig.topper wrote:
> gadi.haber wrote:
> > craig.topper wrote:
> > > Should this account for load latency?
> > yes, according to the SNB architects.
> If it shoudl include load latency shouldn't it have a latency of more than 3? ADDPDrr is in a group with latency 3. So shoudln't ADDPrm be more than 3?
The scheduling model is based on the fact that there are no memory latencies effects, i.e., no cache misses and everything is in the 1st level cache.
This is the model successfully used and constantly verified by the architects.
The performance measurements we ran support this model.



Repository:
  rL LLVM

https://reviews.llvm.org/D36663