[PATCH] D36663: [X86][Haswell] Updating HSW instruction scheduling information

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

I think the following are missing from the HWWriteResGroups

IMUL32rmi    2 uops
IMUL32rmi8   2 uops
IMUL32rri    1 uop
IMUL32rri8   1 uop
IMUL64rmi32  2 uops
IMUL64rmi8   2 uops
IMUL64rri32  1 uop
IMUL64rri8   1 uop



================
Comment at: lib/Target/X86/X86SchedHaswell.td:2748
+def: InstRW<[HWWriteResGroup52], (instregex "IMUL(16|32|64)m")>;
+def: InstRW<[HWWriteResGroup52], (instregex "IMUL(16|32|64)rm")>;
+def: InstRW<[HWWriteResGroup52], (instregex "IMUL8m")>;
----------------
I believe believe this

IMUL8m - 2 uops
IMUL16m - 5 uops
IMUL32m - 4 uops
IMUL64m - 3 uops


================
Comment at: lib/Target/X86/X86SchedHaswell.td:2762
+def: InstRW<[HWWriteResGroup52], (instregex "MMX_CVTTPS2PIirm")>;
+def: InstRW<[HWWriteResGroup52], (instregex "MUL(16|32|64)m")>;
+def: InstRW<[HWWriteResGroup52], (instregex "MUL8m")>;
----------------
I believe this

MUL8m - 2 uops
MUL16m - 5 uops
MUL32m - 4 uops
MUL64m - 3 uops


================
Comment at: lib/Target/X86/X86SchedHaswell.td:3156
+}
+def: InstRW<[HWWriteResGroup74], (instregex "IMUL(16|32|64)r")>;
+def: InstRW<[HWWriteResGroup74], (instregex "MUL(16|32|64)r")>;
----------------
Can you recheck this. I believe the following

MUL16r/IMUL16r - 4 uops
MUL32r/IMUL32r - 3 uops
IMUL64r/IMUL64r - 2 uops
MULX64rr - 2 uops


Repository:
  rL LLVM

https://reviews.llvm.org/D36663