[PATCH] D36866: [ARM] Add PostRAScheduling option

[Sam Parker via Phabricator via llvm-commits]

samparker created this revision.
Herald added subscribers: kristof.beyls, javed.absar, aemerson.

https://reviews.llvm.org/D35935 added an option for selecting the machine scheduler for ARM. This patch adds the option to allow also using the post ra scheduler, which brings the ARM backend inline with AArch64 targets. The SchedModel can also set 'PostRAScheduler', as the R52 does, so also query this property in the overridden function.


https://reviews.llvm.org/D36866

Files:
  lib/Target/ARM/ARM.td
  lib/Target/ARM/ARMSubtarget.cpp
  lib/Target/ARM/ARMSubtarget.h


Index: lib/Target/ARM/ARMSubtarget.h
===================================================================
--- lib/Target/ARM/ARMSubtarget.h
+++ lib/Target/ARM/ARMSubtarget.h
@@ -191,6 +191,10 @@
   /// UseMISched - True if MachineScheduler should be used for this subtarget.
   bool UseMISched = false;
 
+  /// UsePostRAScheduler - True if scheduling should happen again after
+  /// register allocation.
+  bool UsePostRAScheduler = false;
+
   /// HasThumb2 - True if Thumb2 instructions are supported.
   bool HasThumb2 = false;
 
@@ -660,6 +664,7 @@
   bool isRWPI() const;
 
   bool useMachineScheduler() const { return UseMISched; }
+  bool usePostRAScheduler() const { return UsePostRAScheduler; }
   bool useSoftFloat() const { return UseSoftFloat; }
   bool isThumb() const { return InThumbMode; }
   bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
Index: lib/Target/ARM/ARMSubtarget.cpp
===================================================================
--- lib/Target/ARM/ARMSubtarget.cpp
+++ lib/Target/ARM/ARMSubtarget.cpp
@@ -357,6 +357,10 @@
 
 // This overrides the PostRAScheduler bit in the SchedModel for any CPU.
 bool ARMSubtarget::enablePostRAScheduler() const {
+  if (usePostRAScheduler())
+    return true;
+  if (SchedModel.PostRAScheduler)
+    return true;
   // No need for PostRA scheduling on subtargets where we use the
   // MachineScheduler.
   if (useMachineScheduler())
Index: lib/Target/ARM/ARM.td
===================================================================
--- lib/Target/ARM/ARM.td
+++ lib/Target/ARM/ARM.td
@@ -323,6 +323,9 @@
 def FeatureUseMISched: SubtargetFeature<"use-misched", "UseMISched", "true",
                                         "Use the MachineScheduler">;
 
+def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
+    "UsePostRAScheduler", "true", "Schedule again after register allocation">;
+
 //===----------------------------------------------------------------------===//
 // ARM architecture class
 //
@@ -869,7 +872,8 @@
 
 def : ProcessorModel<"cortex-m3", CortexM3Model,        [ARMv7m,
                                                          ProcM3,
-                                                         FeatureHasNoBranchPredictor]>;
+                                                         FeatureHasNoBranchPredictor,
+                                                         FeaturePostRAScheduler]>;
 
 def : ProcessorModel<"sc300",     CortexM3Model,        [ARMv7m,
                                                          ProcM3,
@@ -879,11 +883,13 @@
                                                          FeatureVFP4,
                                                          FeatureVFPOnlySP,
                                                          FeatureD16,
-                                                         FeatureHasNoBranchPredictor]>;
+                                                         FeatureHasNoBranchPredictor,
+                                                         FeaturePostRAScheduler]>;
 
 def : ProcNoItin<"cortex-m7",                           [ARMv7em,
                                                          FeatureFPARMv8,
-                                                         FeatureD16]>;
+                                                         FeatureD16,
+                                                         FeaturePostRAScheduler]>;
 
 def : ProcNoItin<"cortex-m23",                          [ARMv8mBaseline,
                                                          FeatureNoMovt]>;
@@ -893,7 +899,8 @@
                                                          FeatureFPARMv8,
                                                          FeatureD16,
                                                          FeatureVFPOnlySP,
-                                                         FeatureHasNoBranchPredictor]>;
+                                                         FeatureHasNoBranchPredictor,
+                                                         FeaturePostRAScheduler]>;
 
 def : ProcNoItin<"cortex-a32",                           [ARMv8a,
                                                          FeatureHWDivThumb,


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D36866.111642.patch
Type: text/x-patch
Size: 4221 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20170818/32e07d9e/attachment.bin>