[PATCH] D36671: debuginfo: Improve line info when translating a CaseBlock to SDNodes

[Frej Drejhammar via Phabricator via llvm-commits]

frej added inline comments.


================
Comment at: llvm/test/CodeGen/X86/debugloc-no-line-0.ll:1
+; RUN: llc -O0 -mtriple=x86_64-unknown-linux-gnu -o - %s | FileCheck %s
+define i32 @main() !dbg !12 {
----------------
aprantl wrote:
> frej wrote:
> > aprantl wrote:
> > > rather than compiling all the way down to assembler, could this be done with -stop (e.g. -stop-before-regalloc or -stop-after-livedebugvariables) so the test case becomes less fragile?
> > I had a look at checking the mir-code, this exceeds my FileCheck-fu. Instead of just checking for the absence of a ".loc 1 0"-line I would have to check that each "real" instruction has a debug-location. Any pointers on how I should go about this? How do I distinguish "real" instructions from the IMPLICIT_DEFs, labels and successor info? If I hard-code the expected instructions I would expect it to be much more brittle than the current version checking the assembly.
> Could you paste the MIR output with and without your patch? I'm happy to help with crafting the CHECKs.
Sure!

Without the patch

```
name:            main
alignment:       4
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:
  - { id: 0, class: gr32, preferred-register: '' }
  - { id: 1, class: gr32, preferred-register: '' }
  - { id: 2, class: gr32, preferred-register: '' }
  - { id: 3, class: gr32, preferred-register: '' }
  - { id: 4, class: gr32, preferred-register: '' }
  - { id: 5, class: gr32, preferred-register: '' }
liveins:
frameInfo:
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       0
  offsetAdjustment: 0
  maxAlignment:    0
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  maxCallFrameSize: 4294967295
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  savePoint:       ''
  restorePoint:    ''
fixedStack:
stack:
constants:
body:             |
  bb.0.entry:
    successors: %bb.1.sw.bb(0x40000000), %bb.4.entry(0x40000000)

    %1 = IMPLICIT_DEF
    %0 = COPY %1, debug-location !11
    %3 = IMPLICIT_DEF
    %2 = COPY %3, debug-location !11
    %2 = SUB32ri8 %2, 1, implicit-def %eflags, debug-location !11
    JE_1 %bb.1.sw.bb, implicit %eflags, debug-location !11
    JMP_1 %bb.4.entry, debug-location !11

  bb.4.entry:
    successors: %bb.2.sw.bb2(0x40000000), %bb.3.sw.epilog(0x40000000)

    %4 = COPY %0
    %4 = SUB32ri8 %4, 2, implicit-def %eflags
    JE_1 %bb.2.sw.bb2, implicit %eflags
    JMP_1 %bb.3.sw.epilog

  bb.1.sw.bb:
    successors: %bb.3.sw.epilog(0x80000000)

    JMP_1 %bb.3.sw.epilog, debug-location !12

  bb.2.sw.bb2:
    successors: %bb.3.sw.epilog(0x80000000)

    JMP_1 %bb.3.sw.epilog, debug-location !14

  bb.3.sw.epilog:
    %5 = MOV32ri 4711
    %eax = COPY %5, debug-location !15
    RETQ implicit %eax, debug-location !15

```

With the patch:

```
name:            main
alignment:       4
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:
  - { id: 0, class: gr32, preferred-register: '' }
  - { id: 1, class: gr32, preferred-register: '' }
  - { id: 2, class: gr32, preferred-register: '' }
  - { id: 3, class: gr32, preferred-register: '' }
  - { id: 4, class: gr32, preferred-register: '' }
  - { id: 5, class: gr32, preferred-register: '' }
liveins:
frameInfo:
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       0
  offsetAdjustment: 0
  maxAlignment:    0
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  maxCallFrameSize: 4294967295
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  savePoint:       ''
  restorePoint:    ''
fixedStack:
stack:
constants:
body:             |
  bb.0.entry:
    successors: %bb.1.sw.bb(0x40000000), %bb.4.entry(0x40000000)

    %1 = IMPLICIT_DEF
    %0 = COPY %1, debug-location !11
    %3 = IMPLICIT_DEF
    %2 = COPY %3, debug-location !11
    %2 = SUB32ri8 %2, 1, implicit-def %eflags, debug-location !11
    JE_1 %bb.1.sw.bb, implicit %eflags, debug-location !11
    JMP_1 %bb.4.entry, debug-location !11

  bb.4.entry:
    successors: %bb.2.sw.bb2(0x40000000), %bb.3.sw.epilog(0x40000000)

    %4 = COPY %0, debug-location !11
    %4 = SUB32ri8 %4, 2, implicit-def %eflags, debug-location !11
    JE_1 %bb.2.sw.bb2, implicit %eflags, debug-location !11
    JMP_1 %bb.3.sw.epilog, debug-location !11

  bb.1.sw.bb:
    successors: %bb.3.sw.epilog(0x80000000)

    JMP_1 %bb.3.sw.epilog, debug-location !12

  bb.2.sw.bb2:
    successors: %bb.3.sw.epilog(0x80000000)

    JMP_1 %bb.3.sw.epilog, debug-location !14

  bb.3.sw.epilog:
    %5 = MOV32ri 4711
    %eax = COPY %5, debug-location !15
    RETQ implicit %eax, debug-location !15

```



Repository:
  rL LLVM

https://reviews.llvm.org/D36671