[PATCH] D36671: debuginfo: Improve line info when translating a CaseBlock to SDNodes

[Adrian Prantl via Phabricator via llvm-commits]

aprantl added inline comments.


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Comment at: llvm/test/CodeGen/X86/debugloc-no-line-0.ll:1
+; RUN: llc -O0 -mtriple=x86_64-unknown-linux-gnu -o - %s | FileCheck %s
+define i32 @main() !dbg !12 {
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frej wrote:
> aprantl wrote:
> > rather than compiling all the way down to assembler, could this be done with -stop (e.g. -stop-before-regalloc or -stop-after-livedebugvariables) so the test case becomes less fragile?
> I had a look at checking the mir-code, this exceeds my FileCheck-fu. Instead of just checking for the absence of a ".loc 1 0"-line I would have to check that each "real" instruction has a debug-location. Any pointers on how I should go about this? How do I distinguish "real" instructions from the IMPLICIT_DEFs, labels and successor info? If I hard-code the expected instructions I would expect it to be much more brittle than the current version checking the assembly.
Could you paste the MIR output with and without your patch? I'm happy to help with crafting the CHECKs.


Repository:
  rL LLVM

https://reviews.llvm.org/D36671