[llvm] r310346 - [PowerPC] Eliminate compares - add i32 sext/zext handling for SETLE/SETGE
Chandler Carruth via llvm-commits
llvm-commits at lists.llvm.org
Sun Aug 13 16:36:54 PDT 2017
This patch appears to be very deeply and fundamentally broken. See below:
On Tue, Aug 8, 2017 at 4:21 AM Nemanja Ivanovic via llvm-commits <
llvm-commits at lists.llvm.org> wrote:
> Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=310346&r1=310345&r2=310346&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Tue Aug 8 04:20:44
> 2017
> @@ -2831,6 +2903,32 @@ SDValue PPCDAGToDAGISel::get32BitZExtCom
> return SDValue(CurDAG->getMachineNode(PPC::XORI, dl, MVT::i32, Shift,
> getI32Imm(1, dl)), 0);
> }
> + case ISD::SETGE: {
> + // (zext (setcc %a, %b, setge)) -> (xor (lshr (sub %a, %b), 63), 1)
> + // (zext (setcc %a, 0, setge)) -> (lshr (~ %a), 31)
> + if(IsRHSZero)
> + return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GEZExt);
> +
> + // Not a special case (i.e. RHS == 0). Handle (%a >= %b) as (%b <= %a)
> + // by swapping inputs and falling through.
> + std::swap(LHS, RHS);
> + ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
> + IsRHSZero = RHSConst && RHSConst->isNullValue();
> + LLVM_FALLTHROUGH;
> + }
> + case ISD::SETLE: {
> + // (zext (setcc %a, %b, setle)) -> (xor (lshr (sub %b, %a), 63), 1)
> + // (zext (setcc %a, 0, setle)) -> (xor (lshr (- %a), 63), 1)
> + if(IsRHSZero)
> + return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LEZExt);
> + SDValue Sub =
> + SDValue(CurDAG->getMachineNode(PPC::SUBF, dl, MVT::i32, LHS, RHS),
> 0);
> + SDValue Shift =
> + SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32, Sub,
> + getI64Imm(1, dl), getI64Imm(63,
> dl)), 0);
>
So, even when operating on a 32-bit values, the RLDICL instruction is
fundamentally a 64-bit operation. It is rotating left a 64-bit quantity and
then clearing the left 63 bits.
The code is using it to extract the high (sign) bit to determine whether
the subtract produced a negative number. But the high (sign) bit is in bit
position 31 not bit position 63. And so rotating left by one bit as this
does will reliably (AFAICT) produce a zero in bit position 0 and will clear
the bits to the left.
In other words, this always produces '0', which means that the 'setle'
always compiles to "true". =[
I have a high-level library implementing saturating arithmetic and it
manages to trigger this reliably. What is worse, it is *extraordinarily*
hard to trigger this particular combine from high level code. I tried for a
long time (about 8 hours across two days) and have not managed to find any
remotely concise way to trigger this. But then, I'm testing remotely on a
PPC machine and not primarily a PPC developer so perhaps you will have a
much better idea than I do about how to test here.
Anyways, replacing the SH operand to RLDICL here with the value '33'
instead of '1' causes my high level tests to pass. But I can't generate
useful test cases here so I don't feel comfortable committing that.
Anyways, I'll probably revert this until a test case can be added. Sorry
for any disruption but hopefully the above analysis makes it easy to fix.
> + return SDValue(CurDAG->getMachineNode(PPC::XORI, dl,
> + MVT::i32, Shift, getI32Imm(1, dl)), 0);
> + }
> }
> }
>
> @@ -2878,6 +2976,34 @@ SDValue PPCDAGToDAGISel::get32BitSExtCom
> getI32Imm(1, dl)), 0);
> return SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Xori),
> 0);
> }
> + case ISD::SETGE: {
> + // (sext (setcc %a, %b, setge)) -> (add (lshr (sub %a, %b), 63), -1)
> + // (sext (setcc %a, 0, setge)) -> (ashr (~ %a), 31)
> + if (IsRHSZero)
> + return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GESExt);
> +
> + // Not a special case (i.e. RHS == 0). Handle (%a >= %b) as (%b <= %a)
> + // by swapping inputs and falling through.
> + std::swap(LHS, RHS);
> + ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
> + IsRHSZero = RHSConst && RHSConst->isNullValue();
> + LLVM_FALLTHROUGH;
> + }
> + case ISD::SETLE: {
> + // (sext (setcc %a, %b, setge)) -> (add (lshr (sub %b, %a), 63), -1)
> + // (sext (setcc %a, 0, setle)) -> (add (lshr (- %a), 63), -1)
> + if (IsRHSZero)
> + return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LESExt);
> + SDValue SUBFNode =
> + SDValue(CurDAG->getMachineNode(PPC::SUBF, dl, MVT::i32, MVT::Glue,
> + LHS, RHS), 0);
> + SDValue Srdi =
> + SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32,
> + SUBFNode, getI64Imm(1, dl),
> + getI64Imm(63, dl)), 0);
> + return SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Srdi,
> + getI32Imm(-1, dl)), 0);
> + }
> }
> }
>
>
> Added: llvm/trunk/test/CodeGen/PowerPC/testComparesigesc.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigesc.ll?rev=310346&view=auto
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/PowerPC/testComparesigesc.ll (added)
> +++ llvm/trunk/test/CodeGen/PowerPC/testComparesigesc.ll Tue Aug 8
> 04:20:44 2017
> @@ -0,0 +1,68 @@
> +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2
> \
> +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
> +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd
> --implicit-check-not cmpl
> +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu
> -O2 \
> +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
> +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd
> --implicit-check-not cmpl
> +; NOTE: Assertions have been autogenerated by
> utils/update_llc_test_checks.py
> + at glob = common local_unnamed_addr global i8 0, align 1
> +
> +define signext i32 @test_igesc(i8 signext %a, i8 signext %b) {
> +; CHECK-LABEL: test_igesc:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: subf r3, r4, r3
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: xori r3, r3, 1
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sge i8 %a, %b
> + %conv2 = zext i1 %cmp to i32
> + ret i32 %conv2
> +}
> +
> +define signext i32 @test_igesc_sext(i8 signext %a, i8 signext %b) {
> +; CHECK-LABEL: test_igesc_sext:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: subf r3, r4, r3
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: addi r3, r3, -1
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sge i8 %a, %b
> + %sub = sext i1 %cmp to i32
> + ret i32 %sub
> +}
> +
> +define void @test_igesc_store(i8 signext %a, i8 signext %b) {
> +; CHECK-LABEL: test_igesc_store:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
> +; CHECK-NEXT: subf r3, r4, r3
> +; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: xori r3, r3, 1
> +; CHECK-NEXT: stb r3, 0(r12)
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sge i8 %a, %b
> + %conv3 = zext i1 %cmp to i8
> + store i8 %conv3, i8* @glob, align 1
> + ret void
> +}
> +
> +define void @test_igesc_sext_store(i8 signext %a, i8 signext %b) {
> +; CHECK-LABEL: test_igesc_sext_store:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
> +; CHECK-NEXT: subf r3, r4, r3
> +; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: addi r3, r3, -1
> +; CHECK-NEXT: stb r3, 0(r12)
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sge i8 %a, %b
> + %conv3 = sext i1 %cmp to i8
> + store i8 %conv3, i8* @glob, align 1
> + ret void
> +}
>
> Added: llvm/trunk/test/CodeGen/PowerPC/testComparesigesi.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigesi.ll?rev=310346&view=auto
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/PowerPC/testComparesigesi.ll (added)
> +++ llvm/trunk/test/CodeGen/PowerPC/testComparesigesi.ll Tue Aug 8
> 04:20:44 2017
> @@ -0,0 +1,68 @@
> +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2
> \
> +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
> +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd
> --implicit-check-not cmpl
> +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu
> -O2 \
> +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
> +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd
> --implicit-check-not cmpl
> +; NOTE: Assertions have been autogenerated by
> utils/update_llc_test_checks.py
> + at glob = common local_unnamed_addr global i32 0, align 4
> +
> +define signext i32 @test_igesi(i32 signext %a, i32 signext %b) {
> +; CHECK-LABEL: test_igesi:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: subf r3, r4, r3
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: xori r3, r3, 1
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sge i32 %a, %b
> + %conv = zext i1 %cmp to i32
> + ret i32 %conv
> +}
> +
> +define signext i32 @test_igesi_sext(i32 signext %a, i32 signext %b) {
> +; CHECK-LABEL: test_igesi_sext:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: subf r3, r4, r3
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: addi r3, r3, -1
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sge i32 %a, %b
> + %sub = sext i1 %cmp to i32
> + ret i32 %sub
> +}
> +
> +define void @test_igesi_store(i32 signext %a, i32 signext %b) {
> +; CHECK-LABEL: test_igesi_store:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
> +; CHECK-NEXT: subf r3, r4, r3
> +; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: xori r3, r3, 1
> +; CHECK-NEXT: stw r3, 0(r12)
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sge i32 %a, %b
> + %conv = zext i1 %cmp to i32
> + store i32 %conv, i32* @glob, align 4
> + ret void
> +}
> +
> +define void @test_igesi_sext_store(i32 signext %a, i32 signext %b) {
> +; CHECK-LABEL: test_igesi_sext_store:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
> +; CHECK-NEXT: subf r3, r4, r3
> +; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: addi r3, r3, -1
> +; CHECK-NEXT: stw r3, 0(r12)
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sge i32 %a, %b
> + %sub = sext i1 %cmp to i32
> + store i32 %sub, i32* @glob, align 4
> + ret void
> +}
>
> Added: llvm/trunk/test/CodeGen/PowerPC/testComparesigess.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigess.ll?rev=310346&view=auto
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/PowerPC/testComparesigess.ll (added)
> +++ llvm/trunk/test/CodeGen/PowerPC/testComparesigess.ll Tue Aug 8
> 04:20:44 2017
> @@ -0,0 +1,68 @@
> +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2
> \
> +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
> +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd
> --implicit-check-not cmpl
> +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu
> -O2 \
> +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
> +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd
> --implicit-check-not cmpl
> +; NOTE: Assertions have been autogenerated by
> utils/update_llc_test_checks.py
> + at glob = common local_unnamed_addr global i16 0, align 2
> +
> +define signext i32 @test_igess(i16 signext %a, i16 signext %b) {
> +; CHECK-LABEL: test_igess:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: subf r3, r4, r3
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: xori r3, r3, 1
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sge i16 %a, %b
> + %conv2 = zext i1 %cmp to i32
> + ret i32 %conv2
> +}
> +
> +define signext i32 @test_igess_sext(i16 signext %a, i16 signext %b) {
> +; CHECK-LABEL: test_igess_sext:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: subf r3, r4, r3
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: addi r3, r3, -1
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sge i16 %a, %b
> + %sub = sext i1 %cmp to i32
> + ret i32 %sub
> +}
> +
> +define void @test_igess_store(i16 signext %a, i16 signext %b) {
> +; CHECK-LABEL: test_igess_store:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
> +; CHECK-NEXT: subf r3, r4, r3
> +; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: xori r3, r3, 1
> +; CHECK-NEXT: sth r3, 0(r12)
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sge i16 %a, %b
> + %conv3 = zext i1 %cmp to i16
> + store i16 %conv3, i16* @glob, align 2
> + ret void
> +}
> +
> +define void @test_igess_sext_store(i16 signext %a, i16 signext %b) {
> +; CHECK-LABEL: test_igess_sext_store:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
> +; CHECK-NEXT: subf r3, r4, r3
> +; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: addi r3, r3, -1
> +; CHECK-NEXT: sth r3, 0(r12)
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sge i16 %a, %b
> + %conv3 = sext i1 %cmp to i16
> + store i16 %conv3, i16* @glob, align 2
> + ret void
> +}
>
> Added: llvm/trunk/test/CodeGen/PowerPC/testComparesilesc.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesilesc.ll?rev=310346&view=auto
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/PowerPC/testComparesilesc.ll (added)
> +++ llvm/trunk/test/CodeGen/PowerPC/testComparesilesc.ll Tue Aug 8
> 04:20:44 2017
> @@ -0,0 +1,68 @@
> +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2
> \
> +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
> +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd
> --implicit-check-not cmpl
> +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu
> -O2 \
> +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
> +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd
> --implicit-check-not cmpl
> +; NOTE: Assertions have been autogenerated by
> utils/update_llc_test_checks.py
> + at glob = common local_unnamed_addr global i8 0, align 1
> +
> +define signext i32 @test_ilesc(i8 signext %a, i8 signext %b) {
> +; CHECK-LABEL: test_ilesc:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: subf r3, r3, r4
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: xori r3, r3, 1
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sle i8 %a, %b
> + %conv2 = zext i1 %cmp to i32
> + ret i32 %conv2
> +}
> +
> +define signext i32 @test_ilesc_sext(i8 signext %a, i8 signext %b) {
> +; CHECK-LABEL: test_ilesc_sext:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: subf r3, r3, r4
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: addi r3, r3, -1
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sle i8 %a, %b
> + %sub = sext i1 %cmp to i32
> + ret i32 %sub
> +}
> +
> +define void @test_ilesc_store(i8 signext %a, i8 signext %b) {
> +; CHECK-LABEL: test_ilesc_store:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
> +; CHECK-NEXT: subf r3, r3, r4
> +; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: xori r3, r3, 1
> +; CHECK-NEXT: stb r3, 0(r12)
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sle i8 %a, %b
> + %conv3 = zext i1 %cmp to i8
> + store i8 %conv3, i8* @glob, align 1
> + ret void
> +}
> +
> +define void @test_ilesc_sext_store(i8 signext %a, i8 signext %b) {
> +; CHECK-LABEL: test_ilesc_sext_store:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
> +; CHECK-NEXT: subf r3, r3, r4
> +; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: addi r3, r3, -1
> +; CHECK-NEXT: stb r3, 0(r12)
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sle i8 %a, %b
> + %conv3 = sext i1 %cmp to i8
> + store i8 %conv3, i8* @glob, align 1
> + ret void
> +}
>
> Added: llvm/trunk/test/CodeGen/PowerPC/testComparesilesi.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesilesi.ll?rev=310346&view=auto
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/PowerPC/testComparesilesi.ll (added)
> +++ llvm/trunk/test/CodeGen/PowerPC/testComparesilesi.ll Tue Aug 8
> 04:20:44 2017
> @@ -0,0 +1,68 @@
> +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2
> \
> +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
> +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd
> --implicit-check-not cmpl
> +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu
> -O2 \
> +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
> +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd
> --implicit-check-not cmpl
> +; NOTE: Assertions have been autogenerated by
> utils/update_llc_test_checks.py
> + at glob = common local_unnamed_addr global i32 0, align 4
> +
> +define signext i32 @test_ilesi(i32 signext %a, i32 signext %b) {
> +; CHECK-LABEL: test_ilesi:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: subf r3, r3, r4
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: xori r3, r3, 1
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sle i32 %a, %b
> + %conv = zext i1 %cmp to i32
> + ret i32 %conv
> +}
> +
> +define signext i32 @test_ilesi_sext(i32 signext %a, i32 signext %b) {
> +; CHECK-LABEL: test_ilesi_sext:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: subf r3, r3, r4
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: addi r3, r3, -1
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sle i32 %a, %b
> + %sub = sext i1 %cmp to i32
> + ret i32 %sub
> +}
> +
> +define void @test_ilesi_store(i32 signext %a, i32 signext %b) {
> +; CHECK-LABEL: test_ilesi_store:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
> +; CHECK-NEXT: subf r3, r3, r4
> +; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: xori r3, r3, 1
> +; CHECK-NEXT: stw r3, 0(r12)
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sle i32 %a, %b
> + %conv = zext i1 %cmp to i32
> + store i32 %conv, i32* @glob, align 4
> + ret void
> +}
> +
> +define void @test_ilesi_sext_store(i32 signext %a, i32 signext %b) {
> +; CHECK-LABEL: test_ilesi_sext_store:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
> +; CHECK-NEXT: subf r3, r3, r4
> +; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: addi r3, r3, -1
> +; CHECK-NEXT: stw r3, 0(r12)
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sle i32 %a, %b
> + %sub = sext i1 %cmp to i32
> + store i32 %sub, i32* @glob, align 4
> + ret void
> +}
>
> Added: llvm/trunk/test/CodeGen/PowerPC/testComparesiless.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesiless.ll?rev=310346&view=auto
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/PowerPC/testComparesiless.ll (added)
> +++ llvm/trunk/test/CodeGen/PowerPC/testComparesiless.ll Tue Aug 8
> 04:20:44 2017
> @@ -0,0 +1,68 @@
> +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2
> \
> +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
> +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd
> --implicit-check-not cmpl
> +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu
> -O2 \
> +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
> +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd
> --implicit-check-not cmpl
> +; NOTE: Assertions have been autogenerated by
> utils/update_llc_test_checks.py
> + at glob = common local_unnamed_addr global i16 0, align 2
> +
> +define signext i32 @test_iless(i16 signext %a, i16 signext %b) {
> +; CHECK-LABEL: test_iless:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: subf r3, r3, r4
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: xori r3, r3, 1
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sle i16 %a, %b
> + %conv2 = zext i1 %cmp to i32
> + ret i32 %conv2
> +}
> +
> +define signext i32 @test_iless_sext(i16 signext %a, i16 signext %b) {
> +; CHECK-LABEL: test_iless_sext:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: subf r3, r3, r4
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: addi r3, r3, -1
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sle i16 %a, %b
> + %sub = sext i1 %cmp to i32
> + ret i32 %sub
> +}
> +
> +define void @test_iless_store(i16 signext %a, i16 signext %b) {
> +; CHECK-LABEL: test_iless_store:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
> +; CHECK-NEXT: subf r3, r3, r4
> +; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: xori r3, r3, 1
> +; CHECK-NEXT: sth r3, 0(r12)
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sle i16 %a, %b
> + %conv3 = zext i1 %cmp to i16
> + store i16 %conv3, i16* @glob, align 2
> + ret void
> +}
> +
> +define void @test_iless_sext_store(i16 signext %a, i16 signext %b) {
> +; CHECK-LABEL: test_iless_sext_store:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
> +; CHECK-NEXT: subf r3, r3, r4
> +; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: addi r3, r3, -1
> +; CHECK-NEXT: sth r3, 0(r12)
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sle i16 %a, %b
> + %conv3 = sext i1 %cmp to i16
> + store i16 %conv3, i16* @glob, align 2
> + ret void
> +}
>
> Added: llvm/trunk/test/CodeGen/PowerPC/testComparesllgesc.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllgesc.ll?rev=310346&view=auto
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/PowerPC/testComparesllgesc.ll (added)
> +++ llvm/trunk/test/CodeGen/PowerPC/testComparesllgesc.ll Tue Aug 8
> 04:20:44 2017
> @@ -0,0 +1,68 @@
> +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2
> \
> +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
> +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd
> --implicit-check-not cmpl
> +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu
> -O2 \
> +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
> +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd
> --implicit-check-not cmpl
> +; NOTE: Assertions have been autogenerated by
> utils/update_llc_test_checks.py
> + at glob = common local_unnamed_addr global i8 0, align 1
> +
> +define i64 @test_llgesc(i8 signext %a, i8 signext %b) {
> +; CHECK-LABEL: test_llgesc:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: subf r3, r4, r3
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: xori r3, r3, 1
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sge i8 %a, %b
> + %conv3 = zext i1 %cmp to i64
> + ret i64 %conv3
> +}
> +
> +define i64 @test_llgesc_sext(i8 signext %a, i8 signext %b) {
> +; CHECK-LABEL: test_llgesc_sext:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: subf r3, r4, r3
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: addi r3, r3, -1
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sge i8 %a, %b
> + %conv3 = sext i1 %cmp to i64
> + ret i64 %conv3
> +}
> +
> +define void @test_llgesc_store(i8 signext %a, i8 signext %b) {
> +; CHECK-LABEL: test_llgesc_store:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
> +; CHECK-NEXT: subf r3, r4, r3
> +; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: xori r3, r3, 1
> +; CHECK-NEXT: stb r3, 0(r12)
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sge i8 %a, %b
> + %conv3 = zext i1 %cmp to i8
> + store i8 %conv3, i8* @glob, align 1
> + ret void
> +}
> +
> +define void @test_llgesc_sext_store(i8 signext %a, i8 signext %b) {
> +; CHECK-LABEL: test_llgesc_sext_store:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
> +; CHECK-NEXT: subf r3, r4, r3
> +; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: addi r3, r3, -1
> +; CHECK-NEXT: stb r3, 0(r12)
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sge i8 %a, %b
> + %conv3 = sext i1 %cmp to i8
> + store i8 %conv3, i8* @glob, align 1
> + ret void
> +}
>
> Added: llvm/trunk/test/CodeGen/PowerPC/testComparesllgesi.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllgesi.ll?rev=310346&view=auto
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/PowerPC/testComparesllgesi.ll (added)
> +++ llvm/trunk/test/CodeGen/PowerPC/testComparesllgesi.ll Tue Aug 8
> 04:20:44 2017
> @@ -0,0 +1,68 @@
> +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2
> \
> +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
> +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd
> --implicit-check-not cmpl
> +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu
> -O2 \
> +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
> +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd
> --implicit-check-not cmpl
> +; NOTE: Assertions have been autogenerated by
> utils/update_llc_test_checks.py
> + at glob = common local_unnamed_addr global i32 0, align 4
> +
> +define i64 @test_llgesi(i32 signext %a, i32 signext %b) {
> +; CHECK-LABEL: test_llgesi:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: subf r3, r4, r3
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: xori r3, r3, 1
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sge i32 %a, %b
> + %conv1 = zext i1 %cmp to i64
> + ret i64 %conv1
> +}
> +
> +define i64 @test_llgesi_sext(i32 signext %a, i32 signext %b) {
> +; CHECK-LABEL: test_llgesi_sext:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: subf r3, r4, r3
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: addi r3, r3, -1
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sge i32 %a, %b
> + %conv1 = sext i1 %cmp to i64
> + ret i64 %conv1
> +}
> +
> +define void @test_llgesi_store(i32 signext %a, i32 signext %b) {
> +; CHECK-LABEL: test_llgesi_store:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
> +; CHECK-NEXT: subf r3, r4, r3
> +; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: xori r3, r3, 1
> +; CHECK-NEXT: stw r3, 0(r12)
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sge i32 %a, %b
> + %conv = zext i1 %cmp to i32
> + store i32 %conv, i32* @glob, align 4
> + ret void
> +}
> +
> +define void @test_llgesi_sext_store(i32 signext %a, i32 signext %b) {
> +; CHECK-LABEL: test_llgesi_sext_store:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
> +; CHECK-NEXT: subf r3, r4, r3
> +; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: addi r3, r3, -1
> +; CHECK-NEXT: stw r3, 0(r12)
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sge i32 %a, %b
> + %sub = sext i1 %cmp to i32
> + store i32 %sub, i32* @glob, align 4
> + ret void
> +}
>
> Added: llvm/trunk/test/CodeGen/PowerPC/testComparesllgess.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllgess.ll?rev=310346&view=auto
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/PowerPC/testComparesllgess.ll (added)
> +++ llvm/trunk/test/CodeGen/PowerPC/testComparesllgess.ll Tue Aug 8
> 04:20:44 2017
> @@ -0,0 +1,68 @@
> +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2
> \
> +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
> +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd
> --implicit-check-not cmpl
> +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu
> -O2 \
> +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
> +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd
> --implicit-check-not cmpl
> +; NOTE: Assertions have been autogenerated by
> utils/update_llc_test_checks.py
> + at glob = common local_unnamed_addr global i16 0, align 2
> +
> +define i64 @test_llgess(i16 signext %a, i16 signext %b) {
> +; CHECK-LABEL: test_llgess:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: subf r3, r4, r3
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: xori r3, r3, 1
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sge i16 %a, %b
> + %conv3 = zext i1 %cmp to i64
> + ret i64 %conv3
> +}
> +
> +define i64 @test_llgess_sext(i16 signext %a, i16 signext %b) {
> +; CHECK-LABEL: test_llgess_sext:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: subf r3, r4, r3
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: addi r3, r3, -1
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sge i16 %a, %b
> + %conv3 = sext i1 %cmp to i64
> + ret i64 %conv3
> +}
> +
> +define void @test_llgess_store(i16 signext %a, i16 signext %b) {
> +; CHECK-LABEL: test_llgess_store:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
> +; CHECK-NEXT: subf r3, r4, r3
> +; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: xori r3, r3, 1
> +; CHECK-NEXT: sth r3, 0(r12)
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sge i16 %a, %b
> + %conv3 = zext i1 %cmp to i16
> + store i16 %conv3, i16* @glob, align 2
> + ret void
> +}
> +
> +define void @test_llgess_sext_store(i16 signext %a, i16 signext %b) {
> +; CHECK-LABEL: test_llgess_sext_store:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
> +; CHECK-NEXT: subf r3, r4, r3
> +; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: addi r3, r3, -1
> +; CHECK-NEXT: sth r3, 0(r12)
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sge i16 %a, %b
> + %conv3 = sext i1 %cmp to i16
> + store i16 %conv3, i16* @glob, align 2
> + ret void
> +}
>
> Added: llvm/trunk/test/CodeGen/PowerPC/testCompareslllesc.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testCompareslllesc.ll?rev=310346&view=auto
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/PowerPC/testCompareslllesc.ll (added)
> +++ llvm/trunk/test/CodeGen/PowerPC/testCompareslllesc.ll Tue Aug 8
> 04:20:44 2017
> @@ -0,0 +1,69 @@
> +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2
> \
> +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
> +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd
> --implicit-check-not cmpl
> +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu
> -O2 \
> +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
> +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd
> --implicit-check-not cmpl
> +; NOTE: Assertions have been autogenerated by
> utils/update_llc_test_checks.py
> +
> + at glob = common local_unnamed_addr global i8 0, align 1
> +
> +define i64 @test_lllesc(i8 signext %a, i8 signext %b) {
> +; CHECK-LABEL: test_lllesc:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: subf r3, r3, r4
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: xori r3, r3, 1
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sle i8 %a, %b
> + %conv3 = zext i1 %cmp to i64
> + ret i64 %conv3
> +}
> +
> +define i64 @test_lllesc_sext(i8 signext %a, i8 signext %b) {
> +; CHECK-LABEL: test_lllesc_sext:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: subf r3, r3, r4
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: addi r3, r3, -1
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sle i8 %a, %b
> + %conv3 = sext i1 %cmp to i64
> + ret i64 %conv3
> +}
> +
> +define void @test_lllesc_store(i8 signext %a, i8 signext %b) {
> +; CHECK-LABEL: test_lllesc_store:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
> +; CHECK-NEXT: subf r3, r3, r4
> +; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: xori r3, r3, 1
> +; CHECK-NEXT: stb r3, 0(r12)
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sle i8 %a, %b
> + %conv3 = zext i1 %cmp to i8
> + store i8 %conv3, i8* @glob, align 1
> + ret void
> +}
> +
> +define void @test_lllesc_sext_store(i8 signext %a, i8 signext %b) {
> +; CHECK-LABEL: test_lllesc_sext_store:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
> +; CHECK-NEXT: subf r3, r3, r4
> +; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: addi r3, r3, -1
> +; CHECK-NEXT: stb r3, 0(r12)
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sle i8 %a, %b
> + %conv3 = sext i1 %cmp to i8
> + store i8 %conv3, i8* @glob, align 1
> + ret void
> +}
>
> Added: llvm/trunk/test/CodeGen/PowerPC/testCompareslllesi.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testCompareslllesi.ll?rev=310346&view=auto
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/PowerPC/testCompareslllesi.ll (added)
> +++ llvm/trunk/test/CodeGen/PowerPC/testCompareslllesi.ll Tue Aug 8
> 04:20:44 2017
> @@ -0,0 +1,69 @@
> +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2
> \
> +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
> +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd
> --implicit-check-not cmpl
> +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu
> -O2 \
> +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
> +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd
> --implicit-check-not cmpl
> +; NOTE: Assertions have been autogenerated by
> utils/update_llc_test_checks.py
> +
> + at glob = common local_unnamed_addr global i32 0, align 4
> +
> +define i64 @test_lllesi(i32 signext %a, i32 signext %b) {
> +; CHECK-LABEL: test_lllesi:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: subf r3, r3, r4
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: xori r3, r3, 1
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sle i32 %a, %b
> + %conv1 = zext i1 %cmp to i64
> + ret i64 %conv1
> +}
> +
> +define i64 @test_lllesi_sext(i32 signext %a, i32 signext %b) {
> +; CHECK-LABEL: test_lllesi_sext:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: subf r3, r3, r4
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: addi r3, r3, -1
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sle i32 %a, %b
> + %conv1 = sext i1 %cmp to i64
> + ret i64 %conv1
> +}
> +
> +define void @test_lllesi_store(i32 signext %a, i32 signext %b) {
> +; CHECK-LABEL: test_lllesi_store:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
> +; CHECK-NEXT: subf r3, r3, r4
> +; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: xori r3, r3, 1
> +; CHECK-NEXT: stw r3, 0(r12)
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sle i32 %a, %b
> + %conv = zext i1 %cmp to i32
> + store i32 %conv, i32* @glob, align 4
> + ret void
> +}
> +
> +define void @test_lllesi_sext_store(i32 signext %a, i32 signext %b) {
> +; CHECK-LABEL: test_lllesi_sext_store:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
> +; CHECK-NEXT: subf r3, r3, r4
> +; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: addi r3, r3, -1
> +; CHECK-NEXT: stw r3, 0(r12)
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sle i32 %a, %b
> + %sub = sext i1 %cmp to i32
> + store i32 %sub, i32* @glob, align 4
> + ret void
> +}
>
> Added: llvm/trunk/test/CodeGen/PowerPC/testComparesllless.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllless.ll?rev=310346&view=auto
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/PowerPC/testComparesllless.ll (added)
> +++ llvm/trunk/test/CodeGen/PowerPC/testComparesllless.ll Tue Aug 8
> 04:20:44 2017
> @@ -0,0 +1,69 @@
> +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2
> \
> +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
> +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd
> --implicit-check-not cmpl
> +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu
> -O2 \
> +; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
> +; RUN: --implicit-check-not cmpw --implicit-check-not cmpd
> --implicit-check-not cmpl
> +; NOTE: Assertions have been autogenerated by
> utils/update_llc_test_checks.py
> +
> + at glob = common local_unnamed_addr global i16 0, align 2
> +
> +define i64 @test_llless(i16 signext %a, i16 signext %b) {
> +; CHECK-LABEL: test_llless:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: subf r3, r3, r4
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: xori r3, r3, 1
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sle i16 %a, %b
> + %conv3 = zext i1 %cmp to i64
> + ret i64 %conv3
> +}
> +
> +define i64 @test_llless_sext(i16 signext %a, i16 signext %b) {
> +; CHECK-LABEL: test_llless_sext:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: subf r3, r3, r4
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: addi r3, r3, -1
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sle i16 %a, %b
> + %conv3 = sext i1 %cmp to i64
> + ret i64 %conv3
> +}
> +
> +define void @test_llless_store(i16 signext %a, i16 signext %b) {
> +; CHECK-LABEL: test_llless_store:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
> +; CHECK-NEXT: subf r3, r3, r4
> +; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: xori r3, r3, 1
> +; CHECK-NEXT: sth r3, 0(r12)
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sle i16 %a, %b
> + %conv3 = zext i1 %cmp to i16
> + store i16 %conv3, i16* @glob, align 2
> + ret void
> +}
> +
> +define void @test_llless_sext_store(i16 signext %a, i16 signext %b) {
> +; CHECK-LABEL: test_llless_sext_store:
> +; CHECK: # BB#0: # %entry
> +; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
> +; CHECK-NEXT: subf r3, r3, r4
> +; CHECK-NEXT: ld r12, .LC0 at toc@l(r5)
> +; CHECK-NEXT: rldicl r3, r3, 1, 63
> +; CHECK-NEXT: addi r3, r3, -1
> +; CHECK-NEXT: sth r3, 0(r12)
> +; CHECK-NEXT: blr
> +entry:
> + %cmp = icmp sle i16 %a, %b
> + %conv3 = sext i1 %cmp to i16
> + store i16 %conv3, i16* @glob, align 2
> + ret void
> +}
>
>
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