<div dir="ltr"><div class="gmail_quote"><div>This patch appears to be very deeply and fundamentally broken. See below:</div><div dir="ltr"><br></div><div dir="ltr">On Tue, Aug 8, 2017 at 4:21 AM Nemanja Ivanovic via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=310346&r1=310345&r2=310346&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=310346&r1=310345&r2=310346&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original)<br>
+++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Tue Aug 8 04:20:44 2017<br>@@ -2831,6 +2903,32 @@ SDValue PPCDAGToDAGISel::get32BitZExtCom<br>
return SDValue(CurDAG->getMachineNode(PPC::XORI, dl, MVT::i32, Shift,<br>
getI32Imm(1, dl)), 0);<br>
}<br>
+ case ISD::SETGE: {<br>
+ // (zext (setcc %a, %b, setge)) -> (xor (lshr (sub %a, %b), 63), 1)<br>
+ // (zext (setcc %a, 0, setge)) -> (lshr (~ %a), 31)<br>
+ if(IsRHSZero)<br>
+ return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GEZExt);<br>
+<br>
+ // Not a special case (i.e. RHS == 0). Handle (%a >= %b) as (%b <= %a)<br>
+ // by swapping inputs and falling through.<br>
+ std::swap(LHS, RHS);<br>
+ ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);<br>
+ IsRHSZero = RHSConst && RHSConst->isNullValue();<br>
+ LLVM_FALLTHROUGH;<br>
+ }<br>
+ case ISD::SETLE: {<br>
+ // (zext (setcc %a, %b, setle)) -> (xor (lshr (sub %b, %a), 63), 1)<br>
+ // (zext (setcc %a, 0, setle)) -> (xor (lshr (- %a), 63), 1)<br>
+ if(IsRHSZero)<br>
+ return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LEZExt);<br>
+ SDValue Sub =<br>
+ SDValue(CurDAG->getMachineNode(PPC::SUBF, dl, MVT::i32, LHS, RHS), 0);<br>
+ SDValue Shift =<br>
+ SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32, Sub,<br>
+ getI64Imm(1, dl), getI64Imm(63, dl)), 0);<br></blockquote><div><br></div><div>So, even when operating on a 32-bit values, the RLDICL instruction is fundamentally a 64-bit operation. It is rotating left a 64-bit quantity and then clearing the left 63 bits.</div><div><br></div><div>The code is using it to extract the high (sign) bit to determine whether the subtract produced a negative number. But the high (sign) bit is in bit position 31 not bit position 63. And so rotating left by one bit as this does will reliably (AFAICT) produce a zero in bit position 0 and will clear the bits to the left.</div><div><br></div><div>In other words, this always produces '0', which means that the 'setle' always compiles to "true". =[</div><div><br></div><div>I have a high-level library implementing saturating arithmetic and it manages to trigger this reliably. What is worse, it is *extraordinarily* hard to trigger this particular combine from high level code. I tried for a long time (about 8 hours across two days) and have not managed to find any remotely concise way to trigger this. But then, I'm testing remotely on a PPC machine and not primarily a PPC developer so perhaps you will have a much better idea than I do about how to test here.</div><div><br></div><div>Anyways, replacing the SH operand to RLDICL here with the value '33' instead of '1' causes my high level tests to pass. But I can't generate useful test cases here so I don't feel comfortable committing that.</div><div><br></div><div>Anyways, I'll probably revert this until a test case can be added. Sorry for any disruption but hopefully the above analysis makes it easy to fix.</div><div> <br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
+ return SDValue(CurDAG->getMachineNode(PPC::XORI, dl,<br>
+ MVT::i32, Shift, getI32Imm(1, dl)), 0);<br>
+ }<br>
}<br>
}<br>
<br>
@@ -2878,6 +2976,34 @@ SDValue PPCDAGToDAGISel::get32BitSExtCom<br>
getI32Imm(1, dl)), 0);<br>
return SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Xori), 0);<br>
}<br>
+ case ISD::SETGE: {<br>
+ // (sext (setcc %a, %b, setge)) -> (add (lshr (sub %a, %b), 63), -1)<br>
+ // (sext (setcc %a, 0, setge)) -> (ashr (~ %a), 31)<br>
+ if (IsRHSZero)<br>
+ return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GESExt);<br>
+<br>
+ // Not a special case (i.e. RHS == 0). Handle (%a >= %b) as (%b <= %a)<br>
+ // by swapping inputs and falling through.<br>
+ std::swap(LHS, RHS);<br>
+ ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);<br>
+ IsRHSZero = RHSConst && RHSConst->isNullValue();<br>
+ LLVM_FALLTHROUGH;<br>
+ }<br>
+ case ISD::SETLE: {<br>
+ // (sext (setcc %a, %b, setge)) -> (add (lshr (sub %b, %a), 63), -1)<br>
+ // (sext (setcc %a, 0, setle)) -> (add (lshr (- %a), 63), -1)<br>
+ if (IsRHSZero)<br>
+ return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LESExt);<br>
+ SDValue SUBFNode =<br>
+ SDValue(CurDAG->getMachineNode(PPC::SUBF, dl, MVT::i32, MVT::Glue,<br>
+ LHS, RHS), 0);<br>
+ SDValue Srdi =<br>
+ SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32,<br>
+ SUBFNode, getI64Imm(1, dl),<br>
+ getI64Imm(63, dl)), 0);<br>
+ return SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Srdi,<br>
+ getI32Imm(-1, dl)), 0);<br>
+ }<br>
}<br>
}<br>
<br>
<br>
Added: llvm/trunk/test/CodeGen/PowerPC/testComparesigesc.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigesc.ll?rev=310346&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigesc.ll?rev=310346&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/PowerPC/testComparesigesc.ll (added)<br>
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesigesc.ll Tue Aug 8 04:20:44 2017<br>
@@ -0,0 +1,68 @@<br>
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \<br>
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \<br>
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl<br>
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \<br>
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \<br>
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl<br>
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py<br>
+@glob = common local_unnamed_addr global i8 0, align 1<br>
+<br>
+define signext i32 @test_igesc(i8 signext %a, i8 signext %b) {<br>
+; CHECK-LABEL: test_igesc:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: subf r3, r4, r3<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: xori r3, r3, 1<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sge i8 %a, %b<br>
+ %conv2 = zext i1 %cmp to i32<br>
+ ret i32 %conv2<br>
+}<br>
+<br>
+define signext i32 @test_igesc_sext(i8 signext %a, i8 signext %b) {<br>
+; CHECK-LABEL: test_igesc_sext:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: subf r3, r4, r3<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: addi r3, r3, -1<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sge i8 %a, %b<br>
+ %sub = sext i1 %cmp to i32<br>
+ ret i32 %sub<br>
+}<br>
+<br>
+define void @test_igesc_store(i8 signext %a, i8 signext %b) {<br>
+; CHECK-LABEL: test_igesc_store:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: addis r5, r2, .LC0@toc@ha<br>
+; CHECK-NEXT: subf r3, r4, r3<br>
+; CHECK-NEXT: ld r12, .LC0@toc@l(r5)<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: xori r3, r3, 1<br>
+; CHECK-NEXT: stb r3, 0(r12)<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sge i8 %a, %b<br>
+ %conv3 = zext i1 %cmp to i8<br>
+ store i8 %conv3, i8* @glob, align 1<br>
+ ret void<br>
+}<br>
+<br>
+define void @test_igesc_sext_store(i8 signext %a, i8 signext %b) {<br>
+; CHECK-LABEL: test_igesc_sext_store:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: addis r5, r2, .LC0@toc@ha<br>
+; CHECK-NEXT: subf r3, r4, r3<br>
+; CHECK-NEXT: ld r12, .LC0@toc@l(r5)<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: addi r3, r3, -1<br>
+; CHECK-NEXT: stb r3, 0(r12)<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sge i8 %a, %b<br>
+ %conv3 = sext i1 %cmp to i8<br>
+ store i8 %conv3, i8* @glob, align 1<br>
+ ret void<br>
+}<br>
<br>
Added: llvm/trunk/test/CodeGen/PowerPC/testComparesigesi.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigesi.ll?rev=310346&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigesi.ll?rev=310346&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/PowerPC/testComparesigesi.ll (added)<br>
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesigesi.ll Tue Aug 8 04:20:44 2017<br>
@@ -0,0 +1,68 @@<br>
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \<br>
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \<br>
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl<br>
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \<br>
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \<br>
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl<br>
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py<br>
+@glob = common local_unnamed_addr global i32 0, align 4<br>
+<br>
+define signext i32 @test_igesi(i32 signext %a, i32 signext %b) {<br>
+; CHECK-LABEL: test_igesi:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: subf r3, r4, r3<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: xori r3, r3, 1<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sge i32 %a, %b<br>
+ %conv = zext i1 %cmp to i32<br>
+ ret i32 %conv<br>
+}<br>
+<br>
+define signext i32 @test_igesi_sext(i32 signext %a, i32 signext %b) {<br>
+; CHECK-LABEL: test_igesi_sext:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: subf r3, r4, r3<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: addi r3, r3, -1<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sge i32 %a, %b<br>
+ %sub = sext i1 %cmp to i32<br>
+ ret i32 %sub<br>
+}<br>
+<br>
+define void @test_igesi_store(i32 signext %a, i32 signext %b) {<br>
+; CHECK-LABEL: test_igesi_store:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: addis r5, r2, .LC0@toc@ha<br>
+; CHECK-NEXT: subf r3, r4, r3<br>
+; CHECK-NEXT: ld r12, .LC0@toc@l(r5)<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: xori r3, r3, 1<br>
+; CHECK-NEXT: stw r3, 0(r12)<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sge i32 %a, %b<br>
+ %conv = zext i1 %cmp to i32<br>
+ store i32 %conv, i32* @glob, align 4<br>
+ ret void<br>
+}<br>
+<br>
+define void @test_igesi_sext_store(i32 signext %a, i32 signext %b) {<br>
+; CHECK-LABEL: test_igesi_sext_store:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: addis r5, r2, .LC0@toc@ha<br>
+; CHECK-NEXT: subf r3, r4, r3<br>
+; CHECK-NEXT: ld r12, .LC0@toc@l(r5)<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: addi r3, r3, -1<br>
+; CHECK-NEXT: stw r3, 0(r12)<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sge i32 %a, %b<br>
+ %sub = sext i1 %cmp to i32<br>
+ store i32 %sub, i32* @glob, align 4<br>
+ ret void<br>
+}<br>
<br>
Added: llvm/trunk/test/CodeGen/PowerPC/testComparesigess.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigess.ll?rev=310346&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigess.ll?rev=310346&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/PowerPC/testComparesigess.ll (added)<br>
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesigess.ll Tue Aug 8 04:20:44 2017<br>
@@ -0,0 +1,68 @@<br>
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \<br>
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \<br>
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl<br>
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \<br>
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \<br>
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl<br>
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py<br>
+@glob = common local_unnamed_addr global i16 0, align 2<br>
+<br>
+define signext i32 @test_igess(i16 signext %a, i16 signext %b) {<br>
+; CHECK-LABEL: test_igess:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: subf r3, r4, r3<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: xori r3, r3, 1<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sge i16 %a, %b<br>
+ %conv2 = zext i1 %cmp to i32<br>
+ ret i32 %conv2<br>
+}<br>
+<br>
+define signext i32 @test_igess_sext(i16 signext %a, i16 signext %b) {<br>
+; CHECK-LABEL: test_igess_sext:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: subf r3, r4, r3<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: addi r3, r3, -1<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sge i16 %a, %b<br>
+ %sub = sext i1 %cmp to i32<br>
+ ret i32 %sub<br>
+}<br>
+<br>
+define void @test_igess_store(i16 signext %a, i16 signext %b) {<br>
+; CHECK-LABEL: test_igess_store:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: addis r5, r2, .LC0@toc@ha<br>
+; CHECK-NEXT: subf r3, r4, r3<br>
+; CHECK-NEXT: ld r12, .LC0@toc@l(r5)<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: xori r3, r3, 1<br>
+; CHECK-NEXT: sth r3, 0(r12)<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sge i16 %a, %b<br>
+ %conv3 = zext i1 %cmp to i16<br>
+ store i16 %conv3, i16* @glob, align 2<br>
+ ret void<br>
+}<br>
+<br>
+define void @test_igess_sext_store(i16 signext %a, i16 signext %b) {<br>
+; CHECK-LABEL: test_igess_sext_store:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: addis r5, r2, .LC0@toc@ha<br>
+; CHECK-NEXT: subf r3, r4, r3<br>
+; CHECK-NEXT: ld r12, .LC0@toc@l(r5)<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: addi r3, r3, -1<br>
+; CHECK-NEXT: sth r3, 0(r12)<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sge i16 %a, %b<br>
+ %conv3 = sext i1 %cmp to i16<br>
+ store i16 %conv3, i16* @glob, align 2<br>
+ ret void<br>
+}<br>
<br>
Added: llvm/trunk/test/CodeGen/PowerPC/testComparesilesc.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesilesc.ll?rev=310346&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesilesc.ll?rev=310346&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/PowerPC/testComparesilesc.ll (added)<br>
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesilesc.ll Tue Aug 8 04:20:44 2017<br>
@@ -0,0 +1,68 @@<br>
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \<br>
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \<br>
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl<br>
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \<br>
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \<br>
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl<br>
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py<br>
+@glob = common local_unnamed_addr global i8 0, align 1<br>
+<br>
+define signext i32 @test_ilesc(i8 signext %a, i8 signext %b) {<br>
+; CHECK-LABEL: test_ilesc:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: subf r3, r3, r4<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: xori r3, r3, 1<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sle i8 %a, %b<br>
+ %conv2 = zext i1 %cmp to i32<br>
+ ret i32 %conv2<br>
+}<br>
+<br>
+define signext i32 @test_ilesc_sext(i8 signext %a, i8 signext %b) {<br>
+; CHECK-LABEL: test_ilesc_sext:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: subf r3, r3, r4<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: addi r3, r3, -1<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sle i8 %a, %b<br>
+ %sub = sext i1 %cmp to i32<br>
+ ret i32 %sub<br>
+}<br>
+<br>
+define void @test_ilesc_store(i8 signext %a, i8 signext %b) {<br>
+; CHECK-LABEL: test_ilesc_store:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: addis r5, r2, .LC0@toc@ha<br>
+; CHECK-NEXT: subf r3, r3, r4<br>
+; CHECK-NEXT: ld r12, .LC0@toc@l(r5)<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: xori r3, r3, 1<br>
+; CHECK-NEXT: stb r3, 0(r12)<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sle i8 %a, %b<br>
+ %conv3 = zext i1 %cmp to i8<br>
+ store i8 %conv3, i8* @glob, align 1<br>
+ ret void<br>
+}<br>
+<br>
+define void @test_ilesc_sext_store(i8 signext %a, i8 signext %b) {<br>
+; CHECK-LABEL: test_ilesc_sext_store:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: addis r5, r2, .LC0@toc@ha<br>
+; CHECK-NEXT: subf r3, r3, r4<br>
+; CHECK-NEXT: ld r12, .LC0@toc@l(r5)<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: addi r3, r3, -1<br>
+; CHECK-NEXT: stb r3, 0(r12)<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sle i8 %a, %b<br>
+ %conv3 = sext i1 %cmp to i8<br>
+ store i8 %conv3, i8* @glob, align 1<br>
+ ret void<br>
+}<br>
<br>
Added: llvm/trunk/test/CodeGen/PowerPC/testComparesilesi.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesilesi.ll?rev=310346&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesilesi.ll?rev=310346&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/PowerPC/testComparesilesi.ll (added)<br>
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesilesi.ll Tue Aug 8 04:20:44 2017<br>
@@ -0,0 +1,68 @@<br>
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \<br>
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \<br>
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl<br>
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \<br>
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \<br>
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl<br>
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py<br>
+@glob = common local_unnamed_addr global i32 0, align 4<br>
+<br>
+define signext i32 @test_ilesi(i32 signext %a, i32 signext %b) {<br>
+; CHECK-LABEL: test_ilesi:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: subf r3, r3, r4<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: xori r3, r3, 1<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sle i32 %a, %b<br>
+ %conv = zext i1 %cmp to i32<br>
+ ret i32 %conv<br>
+}<br>
+<br>
+define signext i32 @test_ilesi_sext(i32 signext %a, i32 signext %b) {<br>
+; CHECK-LABEL: test_ilesi_sext:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: subf r3, r3, r4<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: addi r3, r3, -1<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sle i32 %a, %b<br>
+ %sub = sext i1 %cmp to i32<br>
+ ret i32 %sub<br>
+}<br>
+<br>
+define void @test_ilesi_store(i32 signext %a, i32 signext %b) {<br>
+; CHECK-LABEL: test_ilesi_store:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: addis r5, r2, .LC0@toc@ha<br>
+; CHECK-NEXT: subf r3, r3, r4<br>
+; CHECK-NEXT: ld r12, .LC0@toc@l(r5)<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: xori r3, r3, 1<br>
+; CHECK-NEXT: stw r3, 0(r12)<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sle i32 %a, %b<br>
+ %conv = zext i1 %cmp to i32<br>
+ store i32 %conv, i32* @glob, align 4<br>
+ ret void<br>
+}<br>
+<br>
+define void @test_ilesi_sext_store(i32 signext %a, i32 signext %b) {<br>
+; CHECK-LABEL: test_ilesi_sext_store:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: addis r5, r2, .LC0@toc@ha<br>
+; CHECK-NEXT: subf r3, r3, r4<br>
+; CHECK-NEXT: ld r12, .LC0@toc@l(r5)<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: addi r3, r3, -1<br>
+; CHECK-NEXT: stw r3, 0(r12)<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sle i32 %a, %b<br>
+ %sub = sext i1 %cmp to i32<br>
+ store i32 %sub, i32* @glob, align 4<br>
+ ret void<br>
+}<br>
<br>
Added: llvm/trunk/test/CodeGen/PowerPC/testComparesiless.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesiless.ll?rev=310346&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesiless.ll?rev=310346&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/PowerPC/testComparesiless.ll (added)<br>
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesiless.ll Tue Aug 8 04:20:44 2017<br>
@@ -0,0 +1,68 @@<br>
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \<br>
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \<br>
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl<br>
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \<br>
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \<br>
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl<br>
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py<br>
+@glob = common local_unnamed_addr global i16 0, align 2<br>
+<br>
+define signext i32 @test_iless(i16 signext %a, i16 signext %b) {<br>
+; CHECK-LABEL: test_iless:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: subf r3, r3, r4<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: xori r3, r3, 1<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sle i16 %a, %b<br>
+ %conv2 = zext i1 %cmp to i32<br>
+ ret i32 %conv2<br>
+}<br>
+<br>
+define signext i32 @test_iless_sext(i16 signext %a, i16 signext %b) {<br>
+; CHECK-LABEL: test_iless_sext:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: subf r3, r3, r4<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: addi r3, r3, -1<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sle i16 %a, %b<br>
+ %sub = sext i1 %cmp to i32<br>
+ ret i32 %sub<br>
+}<br>
+<br>
+define void @test_iless_store(i16 signext %a, i16 signext %b) {<br>
+; CHECK-LABEL: test_iless_store:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: addis r5, r2, .LC0@toc@ha<br>
+; CHECK-NEXT: subf r3, r3, r4<br>
+; CHECK-NEXT: ld r12, .LC0@toc@l(r5)<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: xori r3, r3, 1<br>
+; CHECK-NEXT: sth r3, 0(r12)<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sle i16 %a, %b<br>
+ %conv3 = zext i1 %cmp to i16<br>
+ store i16 %conv3, i16* @glob, align 2<br>
+ ret void<br>
+}<br>
+<br>
+define void @test_iless_sext_store(i16 signext %a, i16 signext %b) {<br>
+; CHECK-LABEL: test_iless_sext_store:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: addis r5, r2, .LC0@toc@ha<br>
+; CHECK-NEXT: subf r3, r3, r4<br>
+; CHECK-NEXT: ld r12, .LC0@toc@l(r5)<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: addi r3, r3, -1<br>
+; CHECK-NEXT: sth r3, 0(r12)<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sle i16 %a, %b<br>
+ %conv3 = sext i1 %cmp to i16<br>
+ store i16 %conv3, i16* @glob, align 2<br>
+ ret void<br>
+}<br>
<br>
Added: llvm/trunk/test/CodeGen/PowerPC/testComparesllgesc.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllgesc.ll?rev=310346&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllgesc.ll?rev=310346&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllgesc.ll (added)<br>
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllgesc.ll Tue Aug 8 04:20:44 2017<br>
@@ -0,0 +1,68 @@<br>
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \<br>
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \<br>
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl<br>
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \<br>
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \<br>
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl<br>
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py<br>
+@glob = common local_unnamed_addr global i8 0, align 1<br>
+<br>
+define i64 @test_llgesc(i8 signext %a, i8 signext %b) {<br>
+; CHECK-LABEL: test_llgesc:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: subf r3, r4, r3<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: xori r3, r3, 1<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sge i8 %a, %b<br>
+ %conv3 = zext i1 %cmp to i64<br>
+ ret i64 %conv3<br>
+}<br>
+<br>
+define i64 @test_llgesc_sext(i8 signext %a, i8 signext %b) {<br>
+; CHECK-LABEL: test_llgesc_sext:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: subf r3, r4, r3<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: addi r3, r3, -1<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sge i8 %a, %b<br>
+ %conv3 = sext i1 %cmp to i64<br>
+ ret i64 %conv3<br>
+}<br>
+<br>
+define void @test_llgesc_store(i8 signext %a, i8 signext %b) {<br>
+; CHECK-LABEL: test_llgesc_store:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: addis r5, r2, .LC0@toc@ha<br>
+; CHECK-NEXT: subf r3, r4, r3<br>
+; CHECK-NEXT: ld r12, .LC0@toc@l(r5)<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: xori r3, r3, 1<br>
+; CHECK-NEXT: stb r3, 0(r12)<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sge i8 %a, %b<br>
+ %conv3 = zext i1 %cmp to i8<br>
+ store i8 %conv3, i8* @glob, align 1<br>
+ ret void<br>
+}<br>
+<br>
+define void @test_llgesc_sext_store(i8 signext %a, i8 signext %b) {<br>
+; CHECK-LABEL: test_llgesc_sext_store:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: addis r5, r2, .LC0@toc@ha<br>
+; CHECK-NEXT: subf r3, r4, r3<br>
+; CHECK-NEXT: ld r12, .LC0@toc@l(r5)<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: addi r3, r3, -1<br>
+; CHECK-NEXT: stb r3, 0(r12)<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sge i8 %a, %b<br>
+ %conv3 = sext i1 %cmp to i8<br>
+ store i8 %conv3, i8* @glob, align 1<br>
+ ret void<br>
+}<br>
<br>
Added: llvm/trunk/test/CodeGen/PowerPC/testComparesllgesi.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllgesi.ll?rev=310346&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllgesi.ll?rev=310346&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllgesi.ll (added)<br>
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllgesi.ll Tue Aug 8 04:20:44 2017<br>
@@ -0,0 +1,68 @@<br>
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \<br>
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \<br>
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl<br>
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \<br>
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \<br>
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl<br>
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py<br>
+@glob = common local_unnamed_addr global i32 0, align 4<br>
+<br>
+define i64 @test_llgesi(i32 signext %a, i32 signext %b) {<br>
+; CHECK-LABEL: test_llgesi:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: subf r3, r4, r3<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: xori r3, r3, 1<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sge i32 %a, %b<br>
+ %conv1 = zext i1 %cmp to i64<br>
+ ret i64 %conv1<br>
+}<br>
+<br>
+define i64 @test_llgesi_sext(i32 signext %a, i32 signext %b) {<br>
+; CHECK-LABEL: test_llgesi_sext:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: subf r3, r4, r3<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: addi r3, r3, -1<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sge i32 %a, %b<br>
+ %conv1 = sext i1 %cmp to i64<br>
+ ret i64 %conv1<br>
+}<br>
+<br>
+define void @test_llgesi_store(i32 signext %a, i32 signext %b) {<br>
+; CHECK-LABEL: test_llgesi_store:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: addis r5, r2, .LC0@toc@ha<br>
+; CHECK-NEXT: subf r3, r4, r3<br>
+; CHECK-NEXT: ld r12, .LC0@toc@l(r5)<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: xori r3, r3, 1<br>
+; CHECK-NEXT: stw r3, 0(r12)<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sge i32 %a, %b<br>
+ %conv = zext i1 %cmp to i32<br>
+ store i32 %conv, i32* @glob, align 4<br>
+ ret void<br>
+}<br>
+<br>
+define void @test_llgesi_sext_store(i32 signext %a, i32 signext %b) {<br>
+; CHECK-LABEL: test_llgesi_sext_store:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: addis r5, r2, .LC0@toc@ha<br>
+; CHECK-NEXT: subf r3, r4, r3<br>
+; CHECK-NEXT: ld r12, .LC0@toc@l(r5)<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: addi r3, r3, -1<br>
+; CHECK-NEXT: stw r3, 0(r12)<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sge i32 %a, %b<br>
+ %sub = sext i1 %cmp to i32<br>
+ store i32 %sub, i32* @glob, align 4<br>
+ ret void<br>
+}<br>
<br>
Added: llvm/trunk/test/CodeGen/PowerPC/testComparesllgess.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllgess.ll?rev=310346&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllgess.ll?rev=310346&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllgess.ll (added)<br>
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllgess.ll Tue Aug 8 04:20:44 2017<br>
@@ -0,0 +1,68 @@<br>
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \<br>
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \<br>
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl<br>
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \<br>
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \<br>
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl<br>
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py<br>
+@glob = common local_unnamed_addr global i16 0, align 2<br>
+<br>
+define i64 @test_llgess(i16 signext %a, i16 signext %b) {<br>
+; CHECK-LABEL: test_llgess:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: subf r3, r4, r3<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: xori r3, r3, 1<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sge i16 %a, %b<br>
+ %conv3 = zext i1 %cmp to i64<br>
+ ret i64 %conv3<br>
+}<br>
+<br>
+define i64 @test_llgess_sext(i16 signext %a, i16 signext %b) {<br>
+; CHECK-LABEL: test_llgess_sext:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: subf r3, r4, r3<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: addi r3, r3, -1<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sge i16 %a, %b<br>
+ %conv3 = sext i1 %cmp to i64<br>
+ ret i64 %conv3<br>
+}<br>
+<br>
+define void @test_llgess_store(i16 signext %a, i16 signext %b) {<br>
+; CHECK-LABEL: test_llgess_store:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: addis r5, r2, .LC0@toc@ha<br>
+; CHECK-NEXT: subf r3, r4, r3<br>
+; CHECK-NEXT: ld r12, .LC0@toc@l(r5)<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: xori r3, r3, 1<br>
+; CHECK-NEXT: sth r3, 0(r12)<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sge i16 %a, %b<br>
+ %conv3 = zext i1 %cmp to i16<br>
+ store i16 %conv3, i16* @glob, align 2<br>
+ ret void<br>
+}<br>
+<br>
+define void @test_llgess_sext_store(i16 signext %a, i16 signext %b) {<br>
+; CHECK-LABEL: test_llgess_sext_store:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: addis r5, r2, .LC0@toc@ha<br>
+; CHECK-NEXT: subf r3, r4, r3<br>
+; CHECK-NEXT: ld r12, .LC0@toc@l(r5)<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: addi r3, r3, -1<br>
+; CHECK-NEXT: sth r3, 0(r12)<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sge i16 %a, %b<br>
+ %conv3 = sext i1 %cmp to i16<br>
+ store i16 %conv3, i16* @glob, align 2<br>
+ ret void<br>
+}<br>
<br>
Added: llvm/trunk/test/CodeGen/PowerPC/testCompareslllesc.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testCompareslllesc.ll?rev=310346&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testCompareslllesc.ll?rev=310346&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/PowerPC/testCompareslllesc.ll (added)<br>
+++ llvm/trunk/test/CodeGen/PowerPC/testCompareslllesc.ll Tue Aug 8 04:20:44 2017<br>
@@ -0,0 +1,69 @@<br>
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \<br>
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \<br>
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl<br>
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \<br>
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \<br>
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl<br>
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py<br>
+<br>
+@glob = common local_unnamed_addr global i8 0, align 1<br>
+<br>
+define i64 @test_lllesc(i8 signext %a, i8 signext %b) {<br>
+; CHECK-LABEL: test_lllesc:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: subf r3, r3, r4<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: xori r3, r3, 1<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sle i8 %a, %b<br>
+ %conv3 = zext i1 %cmp to i64<br>
+ ret i64 %conv3<br>
+}<br>
+<br>
+define i64 @test_lllesc_sext(i8 signext %a, i8 signext %b) {<br>
+; CHECK-LABEL: test_lllesc_sext:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: subf r3, r3, r4<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: addi r3, r3, -1<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sle i8 %a, %b<br>
+ %conv3 = sext i1 %cmp to i64<br>
+ ret i64 %conv3<br>
+}<br>
+<br>
+define void @test_lllesc_store(i8 signext %a, i8 signext %b) {<br>
+; CHECK-LABEL: test_lllesc_store:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: addis r5, r2, .LC0@toc@ha<br>
+; CHECK-NEXT: subf r3, r3, r4<br>
+; CHECK-NEXT: ld r12, .LC0@toc@l(r5)<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: xori r3, r3, 1<br>
+; CHECK-NEXT: stb r3, 0(r12)<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sle i8 %a, %b<br>
+ %conv3 = zext i1 %cmp to i8<br>
+ store i8 %conv3, i8* @glob, align 1<br>
+ ret void<br>
+}<br>
+<br>
+define void @test_lllesc_sext_store(i8 signext %a, i8 signext %b) {<br>
+; CHECK-LABEL: test_lllesc_sext_store:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: addis r5, r2, .LC0@toc@ha<br>
+; CHECK-NEXT: subf r3, r3, r4<br>
+; CHECK-NEXT: ld r12, .LC0@toc@l(r5)<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: addi r3, r3, -1<br>
+; CHECK-NEXT: stb r3, 0(r12)<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sle i8 %a, %b<br>
+ %conv3 = sext i1 %cmp to i8<br>
+ store i8 %conv3, i8* @glob, align 1<br>
+ ret void<br>
+}<br>
<br>
Added: llvm/trunk/test/CodeGen/PowerPC/testCompareslllesi.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testCompareslllesi.ll?rev=310346&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testCompareslllesi.ll?rev=310346&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/PowerPC/testCompareslllesi.ll (added)<br>
+++ llvm/trunk/test/CodeGen/PowerPC/testCompareslllesi.ll Tue Aug 8 04:20:44 2017<br>
@@ -0,0 +1,69 @@<br>
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \<br>
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \<br>
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl<br>
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \<br>
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \<br>
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl<br>
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py<br>
+<br>
+@glob = common local_unnamed_addr global i32 0, align 4<br>
+<br>
+define i64 @test_lllesi(i32 signext %a, i32 signext %b) {<br>
+; CHECK-LABEL: test_lllesi:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: subf r3, r3, r4<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: xori r3, r3, 1<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sle i32 %a, %b<br>
+ %conv1 = zext i1 %cmp to i64<br>
+ ret i64 %conv1<br>
+}<br>
+<br>
+define i64 @test_lllesi_sext(i32 signext %a, i32 signext %b) {<br>
+; CHECK-LABEL: test_lllesi_sext:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: subf r3, r3, r4<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: addi r3, r3, -1<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sle i32 %a, %b<br>
+ %conv1 = sext i1 %cmp to i64<br>
+ ret i64 %conv1<br>
+}<br>
+<br>
+define void @test_lllesi_store(i32 signext %a, i32 signext %b) {<br>
+; CHECK-LABEL: test_lllesi_store:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: addis r5, r2, .LC0@toc@ha<br>
+; CHECK-NEXT: subf r3, r3, r4<br>
+; CHECK-NEXT: ld r12, .LC0@toc@l(r5)<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: xori r3, r3, 1<br>
+; CHECK-NEXT: stw r3, 0(r12)<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sle i32 %a, %b<br>
+ %conv = zext i1 %cmp to i32<br>
+ store i32 %conv, i32* @glob, align 4<br>
+ ret void<br>
+}<br>
+<br>
+define void @test_lllesi_sext_store(i32 signext %a, i32 signext %b) {<br>
+; CHECK-LABEL: test_lllesi_sext_store:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: addis r5, r2, .LC0@toc@ha<br>
+; CHECK-NEXT: subf r3, r3, r4<br>
+; CHECK-NEXT: ld r12, .LC0@toc@l(r5)<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: addi r3, r3, -1<br>
+; CHECK-NEXT: stw r3, 0(r12)<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sle i32 %a, %b<br>
+ %sub = sext i1 %cmp to i32<br>
+ store i32 %sub, i32* @glob, align 4<br>
+ ret void<br>
+}<br>
<br>
Added: llvm/trunk/test/CodeGen/PowerPC/testComparesllless.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllless.ll?rev=310346&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllless.ll?rev=310346&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllless.ll (added)<br>
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllless.ll Tue Aug 8 04:20:44 2017<br>
@@ -0,0 +1,69 @@<br>
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \<br>
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \<br>
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl<br>
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \<br>
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \<br>
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl<br>
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py<br>
+<br>
+@glob = common local_unnamed_addr global i16 0, align 2<br>
+<br>
+define i64 @test_llless(i16 signext %a, i16 signext %b) {<br>
+; CHECK-LABEL: test_llless:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: subf r3, r3, r4<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: xori r3, r3, 1<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sle i16 %a, %b<br>
+ %conv3 = zext i1 %cmp to i64<br>
+ ret i64 %conv3<br>
+}<br>
+<br>
+define i64 @test_llless_sext(i16 signext %a, i16 signext %b) {<br>
+; CHECK-LABEL: test_llless_sext:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: subf r3, r3, r4<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: addi r3, r3, -1<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sle i16 %a, %b<br>
+ %conv3 = sext i1 %cmp to i64<br>
+ ret i64 %conv3<br>
+}<br>
+<br>
+define void @test_llless_store(i16 signext %a, i16 signext %b) {<br>
+; CHECK-LABEL: test_llless_store:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: addis r5, r2, .LC0@toc@ha<br>
+; CHECK-NEXT: subf r3, r3, r4<br>
+; CHECK-NEXT: ld r12, .LC0@toc@l(r5)<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: xori r3, r3, 1<br>
+; CHECK-NEXT: sth r3, 0(r12)<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sle i16 %a, %b<br>
+ %conv3 = zext i1 %cmp to i16<br>
+ store i16 %conv3, i16* @glob, align 2<br>
+ ret void<br>
+}<br>
+<br>
+define void @test_llless_sext_store(i16 signext %a, i16 signext %b) {<br>
+; CHECK-LABEL: test_llless_sext_store:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: addis r5, r2, .LC0@toc@ha<br>
+; CHECK-NEXT: subf r3, r3, r4<br>
+; CHECK-NEXT: ld r12, .LC0@toc@l(r5)<br>
+; CHECK-NEXT: rldicl r3, r3, 1, 63<br>
+; CHECK-NEXT: addi r3, r3, -1<br>
+; CHECK-NEXT: sth r3, 0(r12)<br>
+; CHECK-NEXT: blr<br>
+entry:<br>
+ %cmp = icmp sle i16 %a, %b<br>
+ %conv3 = sext i1 %cmp to i16<br>
+ store i16 %conv3, i16* @glob, align 2<br>
+ ret void<br>
+}<br>
<br>
<br>
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