[llvm] r310794 - [AVX512] Correct isExtractSubvectorCheap so that it will return the correct answers for extracting 128-bits from a 512-bit vector and for mask registers.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sun Aug 13 10:40:02 PDT 2017
Author: ctopper
Date: Sun Aug 13 10:40:02 2017
New Revision: 310794
URL: http://llvm.org/viewvc/llvm-project?rev=310794&view=rev
Log:
[AVX512] Correct isExtractSubvectorCheap so that it will return the correct answers for extracting 128-bits from a 512-bit vector and for mask registers.
Previously it would not return true for extracting either of the upper quarters of a 512-bit registers.
For mask registers we support extracting anything from index 0. And otherwise we only support extracting the upper half of a register.
Differential Revision: https://reviews.llvm.org/D36638
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=310794&r1=310793&r2=310794&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sun Aug 13 10:40:02 2017
@@ -4579,7 +4579,13 @@ bool X86TargetLowering::isExtractSubvect
if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
return false;
- return (Index == 0 || Index == ResVT.getVectorNumElements());
+ // Mask vectors support all subregister combinations and operations that
+ // extract half of vector.
+ if (ResVT.getVectorElementType() == MVT::i1)
+ return Index = 0 || ((ResVT.getSizeInBits() == SrcVT.getSizeInBits() * 2) &&
+ (Index == ResVT.getVectorNumElements()));
+
+ return (Index % ResVT.getVectorNumElements()) == 0;
}
bool X86TargetLowering::isCheapToSpeculateCttz() const {
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