[llvm] r310793 - [X86][ARM][TargetLowering] Add SrcVT to isExtractSubvectorCheap
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sun Aug 13 10:29:07 PDT 2017
Author: ctopper
Date: Sun Aug 13 10:29:07 2017
New Revision: 310793
URL: http://llvm.org/viewvc/llvm-project?rev=310793&view=rev
Log:
[X86][ARM][TargetLowering] Add SrcVT to isExtractSubvectorCheap
Summary:
Without the SrcVT its hard to know what is really being asked for. For example if your target has 128, 256, and 512 bit vectors. Maybe extracting 128 from 256 is cheap, but maybe extracting 128 from 512 is not.
For x86 we do support extracting a quarter of a 512-bit register. But for i1 vectors we don't have isel patterns for extracting arbitrary pieces. So we need this to have a correct implementation of isExtractSubvectorCheap for mask vectors.
Reviewers: RKSimon, zvi, efriedma
Reviewed By: RKSimon
Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D36649
Modified:
llvm/trunk/include/llvm/Target/TargetLowering.h
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
llvm/trunk/lib/Target/ARM/ARMISelLowering.h
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.h
Modified: llvm/trunk/include/llvm/Target/TargetLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=310793&r1=310792&r2=310793&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetLowering.h (original)
+++ llvm/trunk/include/llvm/Target/TargetLowering.h Sun Aug 13 10:29:07 2017
@@ -2172,11 +2172,12 @@ public:
return false;
}
- /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
- /// with this index. This is needed because EXTRACT_SUBVECTOR usually
- /// has custom lowering that depends on the index of the first element,
- /// and only the target knows which lowering is cheap.
- virtual bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const {
+ /// Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type
+ /// from this source type with this index. This is needed because
+ /// EXTRACT_SUBVECTOR usually has custom lowering that depends on the index of
+ /// the first element, and only the target knows which lowering is cheap.
+ virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
+ unsigned Index) const {
return false;
}
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=310793&r1=310792&r2=310793&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sun Aug 13 10:29:07 2017
@@ -14212,7 +14212,7 @@ SDValue DAGCombiner::createBuildVecShuff
VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ConcatOps);
VecIn2 = SDValue();
} else if (InVT1.getSizeInBits() == VT.getSizeInBits() * 2) {
- if (!TLI.isExtractSubvectorCheap(VT, NumElems))
+ if (!TLI.isExtractSubvectorCheap(VT, InVT1, NumElems))
return SDValue();
if (!VecIn2.getNode()) {
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=310793&r1=310792&r2=310793&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Sun Aug 13 10:29:07 2017
@@ -13402,7 +13402,7 @@ bool ARMTargetLowering::shouldConvertCon
return true;
}
-bool ARMTargetLowering::isExtractSubvectorCheap(EVT ResVT,
+bool ARMTargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
unsigned Index) const {
if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
return false;
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=310793&r1=310792&r2=310793&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Sun Aug 13 10:29:07 2017
@@ -459,7 +459,8 @@ class InstrItineraryData;
/// Return true if EXTRACT_SUBVECTOR is cheap for this result type
/// with this index.
- bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const override;
+ bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
+ unsigned Index) const override;
/// \brief Returns true if an argument of type Ty needs to be passed in a
/// contiguous block of registers in calling convention CallConv.
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=310793&r1=310792&r2=310793&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sun Aug 13 10:29:07 2017
@@ -4574,7 +4574,7 @@ bool X86TargetLowering::shouldConvertCon
return true;
}
-bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
+bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
unsigned Index) const {
if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
return false;
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=310793&r1=310792&r2=310793&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Sun Aug 13 10:29:07 2017
@@ -1036,7 +1036,8 @@ namespace llvm {
/// Return true if EXTRACT_SUBVECTOR is cheap for this result type
/// with this index.
- bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const override;
+ bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
+ unsigned Index) const override;
/// Intel processors have a unified instruction and data cache
const char * getClearCacheBuiltinName() const override {
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