[PATCH] D36650: [X86] WIP support narrowing operations when only a subvector is demanded

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 110865.
craig.topper added a comment.

Fixed a couple issues and got 2 adds narrowed now.

Looks like there's till an issue where we have equivalent extracts from the next add but one is sandwiched in bitcasts and the other isn't. So they don't get CSEd and then inflate the use count of the add.


https://reviews.llvm.org/D36650

Files:
  lib/Target/X86/X86ISelLowering.cpp
  lib/Target/X86/X86InstrAVX512.td
  test/CodeGen/X86/avx512-intrinsics-upgrade.ll
  test/CodeGen/X86/madd.ll
  test/CodeGen/X86/sad.ll
  test/CodeGen/X86/shuffle-vs-trunc-512.ll
  test/CodeGen/X86/vector-half-conversions.ll
  test/CodeGen/X86/x86-interleaved-access.ll

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