[PATCH] D36650: [X86] WIP support narrowing operations when only a subvector is demanded

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.

This is sort of a work in progress to try to see if we can work toward supporting https://reviews.llvm.org/D36454 and other cases where narrowing can give us smaller operations enabling EVEX->VEX.

There are really 2 components to this patch. Combining 2 layers of extract_subvectors/insert_subvectors. And moving a subvector extract through an operation to its inputs.

So far this successfully narrows the final reduction operation in the sad and madd tests. Ideally we'd narrow some of the earlier operations as well.

We also need to support matching horizontal binops from target shuffles in order to convert the final operation to HADD.


https://reviews.llvm.org/D36650

Files:
  lib/Target/X86/X86ISelLowering.cpp
  lib/Target/X86/X86InstrAVX512.td
  test/CodeGen/X86/avx512-intrinsics-upgrade.ll
  test/CodeGen/X86/madd.ll
  test/CodeGen/X86/sad.ll
  test/CodeGen/X86/shuffle-vs-trunc-512.ll
  test/CodeGen/X86/vector-half-conversions.ll
  test/CodeGen/X86/x86-interleaved-access.ll

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