[PATCH] D31951: TableGen support for parametrized register class information

[Krzysztof Parzyszek via Phabricator via llvm-commits]

kparzysz added a comment.

Intrinsics are not handled here because their types are exposed to outside of TableGen, specifically to the front-end.  We have two sets of HVX intrinsics on Hexagon, one for 64-byte and one for 128-byte mode, and they are not going away.  The rest of clang/LLVM would need to be changed to deal with that.  I've tried to handle intrinsics too, but quickly realized that it wouldn't be possible to have that done within the scope of TableGen.

I think that iPTR with different addressing modes could be handled by TableGen. It would probably not fall under this infrastructure, and could actually be simpler.  All we need is to be able to annotate iPTR with the address space somehow, treating the unannotated iPTR as if it had the default address space.


Repository:
  rL LLVM

https://reviews.llvm.org/D31951