[PATCH] D31951: TableGen support for parametrized register class information
David Chisnall via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 10 03:23:31 PDT 2017
theraven added a comment.
Looking forward to this landing, as we currently have some horrible `#ifdefs` to support different register sizes. We also currently have a *really* ugly hack that allows intrinsics that take iPTR to map to multiple types. I wonder if the same infrastructure could be used to allow iPTR to map to multiple types depending on address space?
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