[PATCH] D36381: [MISched] Add enableMachineScheduler function that checks enable-misched.

[Florian Hahn via Phabricator via llvm-commits]

fhahn created this revision.
Herald added subscribers: kristof.beyls, aemerson.

Currently it seems like -enable-misched behaves differently to overriding
SubtargetInfo::enableMachineScheduler. The latter uses the source ordering in
SelectionDAGISel.cpp, while the former uses a more advanced scheduler.

This change updates SelectionDAGISel.cpp and MachineScheduler to use the same
criterion to decide whether to use the MachineScheduler or not. This patch is
work in progress, as quite a few test cases fail. So far I looked into the
ARM test failures and CodeGen/ARM/cortex-a57-misched-basic.ll fails because
the MachineScheduler falls back to source ordering and with -enable-misched the
instructions have been ordered optimally during SelectionDAGISel.

Full list of failing codegen tests:

Failing Tests (14):

  LLVM :: CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll
  LLVM :: CodeGen/AArch64/arm64-aapcs.ll
  LLVM :: CodeGen/AArch64/arm64-abi-varargs.ll
  LLVM :: CodeGen/AArch64/arm64-abi.ll
  LLVM :: CodeGen/AArch64/arm64-abi_align.ll
  LLVM :: CodeGen/AArch64/arm64-misched-multimmo.ll
  LLVM :: CodeGen/AArch64/arm64-vshift.ll
  LLVM :: CodeGen/ARM/cortex-a57-misched-basic.ll
  LLVM :: CodeGen/ARM/misched-fusion-aes.ll
  LLVM :: CodeGen/X86/partial-fold32.ll
  LLVM :: CodeGen/X86/partial-fold64.ll
  LLVM :: CodeGen/X86/pr16031.ll
  LLVM :: CodeGen/X86/win64_alloca_dynalloca.ll
  LLVM :: CodeGen/X86/zext-fold.ll


https://reviews.llvm.org/D36381

Files:
  include/llvm/CodeGen/MachineScheduler.h
  lib/CodeGen/MachineScheduler.cpp
  lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp


Index: lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -42,6 +42,7 @@
 #include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/CodeGen/MachinePassRegistry.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/MachineScheduler.h"
 #include "llvm/CodeGen/MachineValueType.h"
 #include "llvm/CodeGen/SchedulerRegistry.h"
 #include "llvm/CodeGen/SelectionDAG.h"
@@ -251,7 +252,7 @@
     }
 
     if (OptLevel == CodeGenOpt::None ||
-        (ST.enableMachineScheduler() && ST.enableMachineSchedDefaultSched()) ||
+        (enableMachineScheduler(ST) && ST.enableMachineSchedDefaultSched()) ||
         TLI->getSchedulingPreference() == Sched::Source)
       return createSourceListDAGScheduler(IS, OptLevel);
     if (TLI->getSchedulingPreference() == Sched::RegPressure)
Index: lib/CodeGen/MachineScheduler.cpp
===================================================================
--- lib/CodeGen/MachineScheduler.cpp
+++ lib/CodeGen/MachineScheduler.cpp
@@ -262,6 +262,17 @@
     cl::desc("Enable the machine instruction scheduling pass."), cl::init(true),
     cl::Hidden);
 
+namespace llvm {
+bool enableMachineScheduler(const TargetSubtargetInfo &ST) {
+  if (EnableMachineSched.getNumOccurrences()) {
+    if (!EnableMachineSched)
+      return false;
+  } else if (!ST.enableMachineScheduler())
+    return false;
+  return true;
+}
+} // end namespace llvm
+
 static cl::opt<bool> EnablePostRAMachineSched(
     "enable-post-misched",
     cl::desc("Enable the post-ra machine instruction scheduling pass."),
@@ -356,10 +367,7 @@
   if (skipFunction(*mf.getFunction()))
     return false;
 
-  if (EnableMachineSched.getNumOccurrences()) {
-    if (!EnableMachineSched)
-      return false;
-  } else if (!mf.getSubtarget().enableMachineScheduler())
+  if (!enableMachineScheduler(mf.getSubtarget()))
     return false;
 
   DEBUG(dbgs() << "Before MISched:\n"; mf.print(dbgs()));
Index: include/llvm/CodeGen/MachineScheduler.h
===================================================================
--- include/llvm/CodeGen/MachineScheduler.h
+++ include/llvm/CodeGen/MachineScheduler.h
@@ -1032,6 +1032,7 @@
 createCopyConstrainDAGMutation(const TargetInstrInfo *TII,
                                const TargetRegisterInfo *TRI);
 
+bool enableMachineScheduler(const TargetSubtargetInfo &ST);
 } // end namespace llvm
 
 #endif // LLVM_CODEGEN_MACHINESCHEDULER_H


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