[PATCH] D21292: [mips] Correct ELF format for N32.

[Kovacsics Robert via Phabricator via llvm-commits]

KoviRobi added a comment.

After some out-of-band discussions with @Jerryxia32 we've discovered that the problem is that the Mips backend tries to write the 3-in-1 reloc format for N32, but the 32-bit ELF cannot store it all, so it only ends up with the R_MIPS_GPREL16, e.g.
N32 (Clang)

  $ ../build/bin/clang -target mips64 -mabi=n32 -mcpu=mips4 -fpic -fPIC -mabicalls -integrated-as -c test.c -o -|../build/bin/llvm-readobj -r -
  
  File: <stdin>
  Format: ELF32-mips
  Arch: mips
  AddressSize: 32bit
  LoadName: 
  Relocations [
    Section (3) .rela.text {
      0x14 R_MIPS_GPREL16 main 0x0
      0x1C R_MIPS_GPREL16 main 0x0
      0x24 R_MIPS_CALL16 foo 0x0
    }
    Section (6) .rela.pdr {
      0x0 R_MIPS_32 main 0x0
    }
  ]

N64 (Clang)

  $ ../build/bin/clang -target mips64 -mabi=n64 -mcpu=mips4 -fpic -fPIC -mabicalls -integrated-as -c test.c -o -|../build/bin/llvm-readobj -r -
  
  File: <stdin>
  Format: ELF64-mips
  Arch: mips64
  AddressSize: 64bit
  LoadName: 
  Relocations [
    Section (3) .rela.text {
      0x14 R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16 main 0x0
      0x1C R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16 main 0x0
      0x24 R_MIPS_CALL16/R_MIPS_NONE/R_MIPS_NONE foo 0x0
    }
    Section (6) .rela.pdr {
      0x0 R_MIPS_32/R_MIPS_NONE/R_MIPS_NONE main 0x0
    }
  ]

(for the test.c above)

One solution would be to make MipsMCCodeEmitter.cpp emit multiple relocations, but the control flow there is set up to emit one, so it would need some reword to not be confusing, and not trip someone up in the future.

@Jerryxia32  suggested detecting the 3-in-1 relocations when writing the ELF32, and split it. Attached{https://reviews.llvm.org/F4170796} is the diff, with 45 lines of context so it makes more sense and can be read on its own. Perhaps this is better.


https://reviews.llvm.org/D21292