[PATCH] D36104: [AArch64] Coalesce Copy Zero during instruction selection

[Haicheng Wu via Phabricator via llvm-commits]

haicheng added inline comments.


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Comment at: test/CodeGen/AArch64/arm64-addr-type-promotion.ll:31
 ; CHECK-NEXT: ldrb [[LOADEDVAL4:w[0-9]+]], {{\[}}[[BLOCKBASE2]], #2]
+; CHECK-NEXT: mov w0, wzr
 ; CHECK-NEXT: cmp [[LOADEDVAL3]], [[LOADEDVAL4]]
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gberry wrote:
> Is this a regression?
This corresponds to block if.end25.  Do you think it is better to create a new block to sink mov wzr here?  I think neither sinking or not is a clear win since it depends on which path the control flow takes.  Also, the cost of mov wzr can be as cheap as zero.   So, I am bias to keep the current CFG.


Repository:
  rL LLVM

https://reviews.llvm.org/D36104