[PATCH] D36104: [AArch64] Coalesce Copy Zero during instruction selection

[Geoff Berry via Phabricator via llvm-commits]

gberry added inline comments.


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Comment at: lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:2768
+    // If all uses of zero constants are copies to virutal regs, replace the
+    // conatants with WZR/XZR.  Otherwise, materialize zero constants as copies
+    // from WZR/XZR and allow the coalescer to propagate these into other
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Typo: 'conatants' -> 'constants'


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Comment at: test/CodeGen/AArch64/arm64-addr-type-promotion.ll:31
 ; CHECK-NEXT: ldrb [[LOADEDVAL4:w[0-9]+]], {{\[}}[[BLOCKBASE2]], #2]
+; CHECK-NEXT: mov w0, wzr
 ; CHECK-NEXT: cmp [[LOADEDVAL3]], [[LOADEDVAL4]]
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Is this a regression?


Repository:
  rL LLVM

https://reviews.llvm.org/D36104