[llvm] r309584 - Strip trailing whitespace. NFCI.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 31 10:09:27 PDT 2017
Author: rksimon
Date: Mon Jul 31 10:09:27 2017
New Revision: 309584
URL: http://llvm.org/viewvc/llvm-project?rev=309584&view=rev
Log:
Strip trailing whitespace. NFCI.
Modified:
llvm/trunk/lib/Target/X86/X86TargetTransformInfo.cpp
Modified: llvm/trunk/lib/Target/X86/X86TargetTransformInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetTransformInfo.cpp?rev=309584&r1=309583&r2=309584&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86TargetTransformInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86TargetTransformInfo.cpp Mon Jul 31 10:09:27 2017
@@ -144,9 +144,9 @@ int X86TTIImpl::getArithmeticInstrCost(
{ ISD::FSUB, MVT::v2f64, 2 }, // subpd
// v2i64/v4i64 mul is custom lowered as a series of long:
// multiplies(3), shifts(3) and adds(2)
- // slm muldq version throughput is 2 and addq throughput 4
+ // slm muldq version throughput is 2 and addq throughput 4
// thus: 3X2 (muldq throughput) + 3X1 (shift throuput) +
- // 3X4 (addq throughput) = 17
+ // 3X4 (addq throughput) = 17
{ ISD::MUL, MVT::v2i64, 17 },
// slm addq\subq throughput is 4
{ ISD::ADD, MVT::v2i64, 4 },
@@ -2288,7 +2288,7 @@ int X86TTIImpl::getInterleavedMemoryOpCo
unsigned VF = VecTy->getVectorNumElements() / Factor;
Type *ScalarTy = VecTy->getVectorElementType();
-
+
// Calculate the number of memory operations (NumOfMemOps), required
// for load/store the VecTy.
unsigned VecTySize = DL.getTypeStoreSize(VecTy);
@@ -2300,7 +2300,7 @@ int X86TTIImpl::getInterleavedMemoryOpCo
LegalVT.getVectorNumElements());
unsigned MemOpCost =
getMemoryOpCost(Opcode, SingleMemOpTy, Alignment, AddressSpace);
-
+
VectorType *VT = VectorType::get(ScalarTy, VF);
EVT ETy = TLI->getValueType(DL, VT);
if (!ETy.isSimple())
@@ -2320,7 +2320,7 @@ int X86TTIImpl::getInterleavedMemoryOpCo
{ 3, MVT::v8i8, 9 }, //(load 24i8 and) deinterleave into 3 x 8i8
{ 3, MVT::v16i8, 18}, //(load 48i8 and) deinterleave into 3 x 16i8
{ 3, MVT::v32i8, 42 }, //(load 96i8 and) deinterleave into 3 x 32i8
-
+
{ 4, MVT::v2i8, 12 }, //(load 8i8 and) deinterleave into 4 x 2i8
{ 4, MVT::v4i8, 4 }, //(load 16i8 and) deinterleave into 4 x 4i8
{ 4, MVT::v8i8, 20 }, //(load 32i8 and) deinterleave into 4 x 8i8
@@ -2349,7 +2349,7 @@ int X86TTIImpl::getInterleavedMemoryOpCo
} else {
assert(Opcode == Instruction::Store &&
"Expected Store Instruction at this point");
- if (const auto *Entry =
+ if (const auto *Entry =
CostTableLookup(AVX2InterleavedStoreTbl, Factor, ETy.getSimpleVT()))
return NumOfMemOps * MemOpCost + Entry->Cost;
}
@@ -2469,7 +2469,7 @@ int X86TTIImpl::getInterleavedMemoryOpCo
if (ST->hasAVX2())
return getInterleavedMemoryOpCostAVX2(Opcode, VecTy, Factor, Indices,
Alignment, AddressSpace);
-
+
return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
Alignment, AddressSpace);
}
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