[PATCH] D35737: [GSel]: Support Widening G_ICMP's destination operand.
Aditya Nandakumar via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 26 16:07:11 PDT 2017
aditya_nandakumar updated this revision to Diff 108382.
aditya_nandakumar added a comment.
Updated based on feedback.
https://reviews.llvm.org/D35737
Files:
lib/CodeGen/GlobalISel/LegalizerHelper.cpp
Index: lib/CodeGen/GlobalISel/LegalizerHelper.cpp
===================================================================
--- lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -597,22 +597,58 @@
MI.eraseFromParent();
return Legalized;
}
+ case TargetOpcode::G_FCMP: {
+ unsigned Op0Ext, Op1Ext, DstReg;
+ unsigned Cmp1 = MI.getOperand(2).getReg();
+ unsigned Cmp2 = MI.getOperand(3).getReg();
+ if (TypeIdx == 0) {
+ Op0Ext = Cmp1;
+ Op1Ext = Cmp2;
+ DstReg = MRI.createGenericVirtualRegister(WideTy);
+ } else {
+ Op0Ext = MRI.createGenericVirtualRegister(WideTy);
+ Op1Ext = MRI.createGenericVirtualRegister(WideTy);
+ DstReg = MI.getOperand(0).getReg();
+ MIRBuilder.buildInstr(TargetOpcode::G_FPEXT, Op0Ext, Cmp1);
+ MIRBuilder.buildInstr(TargetOpcode::G_FPEXT, Op1Ext, Cmp2);
+ }
+ MIRBuilder.buildFCmp(
+ static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()),
+ DstReg, Op0Ext, Op1Ext);
+ if (TypeIdx == 0)
+ MIRBuilder.buildInstr(TargetOpcode::G_TRUNC, MI.getOperand(0).getReg(),
+ DstReg);
+ MI.eraseFromParent();
+ return Legalized;
+ }
case TargetOpcode::G_ICMP: {
- assert(TypeIdx == 1 && "unable to legalize predicate");
bool IsSigned = CmpInst::isSigned(
static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()));
- unsigned Op0Ext = MRI.createGenericVirtualRegister(WideTy);
- unsigned Op1Ext = MRI.createGenericVirtualRegister(WideTy);
- if (IsSigned) {
- MIRBuilder.buildSExt(Op0Ext, MI.getOperand(2).getReg());
- MIRBuilder.buildSExt(Op1Ext, MI.getOperand(3).getReg());
+ unsigned Cmp1 = MI.getOperand(2).getReg();
+ unsigned Cmp2 = MI.getOperand(3).getReg();
+ unsigned Op0Ext, Op1Ext, DstReg;
+ if (TypeIdx == 0) {
+ Op0Ext = Cmp1;
+ Op1Ext = Cmp2;
+ DstReg = MRI.createGenericVirtualRegister(WideTy);
} else {
- MIRBuilder.buildZExt(Op0Ext, MI.getOperand(2).getReg());
- MIRBuilder.buildZExt(Op1Ext, MI.getOperand(3).getReg());
+ Op0Ext = MRI.createGenericVirtualRegister(WideTy);
+ Op1Ext = MRI.createGenericVirtualRegister(WideTy);
+ DstReg = MI.getOperand(0).getReg();
+ if (IsSigned) {
+ MIRBuilder.buildSExt(Op0Ext, Cmp1);
+ MIRBuilder.buildSExt(Op1Ext, Cmp2);
+ } else {
+ MIRBuilder.buildZExt(Op0Ext, Cmp1);
+ MIRBuilder.buildZExt(Op1Ext, Cmp2);
+ }
}
MIRBuilder.buildICmp(
static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()),
- MI.getOperand(0).getReg(), Op0Ext, Op1Ext);
+ DstReg, Op0Ext, Op1Ext);
+ if (TypeIdx == 0)
+ MIRBuilder.buildInstr(TargetOpcode::G_TRUNC, MI.getOperand(0).getReg(),
+ DstReg);
MI.eraseFromParent();
return Legalized;
}
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