[llvm] r308818 - [X86] Add nopq instruction which is a rex encoded version of nopl for gas compatibility.

[Craig Topper via llvm-commits]

Author: ctopper
Date: Fri Jul 21 18:30:53 2017
New Revision: 308818

URL: http://llvm.org/viewvc/llvm-project?rev=308818&view=rev
Log:
[X86] Add nopq instruction which is a rex encoded version of nopl for gas compatibility.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrInfo.td
    llvm/trunk/test/MC/Disassembler/X86/x86-64.txt
    llvm/trunk/test/MC/X86/x86-32-coverage.s
    llvm/trunk/test/MC/X86/x86-64.s

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=308818&r1=308817&r2=308818&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Fri Jul 21 18:30:53 2017
@@ -1108,11 +1108,15 @@ let hasSideEffects = 0, SchedRW = [Write
                 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize16;
   def NOOPL : I<0x1f, MRMXm, (outs), (ins i32mem:$zero),
                 "nop{l}\t$zero", [], IIC_NOP>, TB, OpSize32;
+  def NOOPQ : RI<0x1f, MRMXm, (outs), (ins i64mem:$zero),
+                "nop{q}\t$zero", [], IIC_NOP>, TB;
   // Also allow register so we can assemble/disassemble
   def NOOPWr : I<0x1f, MRMXr, (outs), (ins GR16:$zero),
                  "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize16;
   def NOOPLr : I<0x1f, MRMXr, (outs), (ins GR32:$zero),
                  "nop{l}\t$zero", [], IIC_NOP>, TB, OpSize32;
+  def NOOPQr : RI<0x1f, MRMXr, (outs), (ins GR64:$zero),
+                  "nop{q}\t$zero", [], IIC_NOP>, TB;
 }
 
 

Modified: llvm/trunk/test/MC/Disassembler/X86/x86-64.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/x86-64.txt?rev=308818&r1=308817&r2=308818&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/x86-64.txt (original)
+++ llvm/trunk/test/MC/Disassembler/X86/x86-64.txt Fri Jul 21 18:30:53 2017
@@ -480,3 +480,9 @@
 
 # CHECK: lwpval $2309737967, (%esp), %edx
 0x67 0x8f 0xea 0x68 0x12 0x0c 0x24 0xef 0xcd 0xab 0x89
+
+# CHECK: nopq -559038737(%rbx,%rcx,8)
+0x48 0x0f 0x1f 0x84 0xcb 0xef 0xbe 0xad 0xde
+
+# CHECK: nopq %rax
+0x48 0x0f 0x1f 0xC0

Modified: llvm/trunk/test/MC/X86/x86-32-coverage.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-32-coverage.s?rev=308818&r1=308817&r2=308818&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86-32-coverage.s (original)
+++ llvm/trunk/test/MC/X86/x86-32-coverage.s Fri Jul 21 18:30:53 2017
@@ -2055,6 +2055,7 @@
 // CHECK:  encoding: [0x0f,0x1f,0x84,0xcb,0xef,0xbe,0xad,0xde]
         	nopl	0xdeadbeef(%ebx,%ecx,8)
 
+
 // CHECK: nopw	32493
 // CHECK:  encoding: [0x66,0x0f,0x1f,0x05,0xed,0x7e,0x00,0x00]
         	nopw	0x7eed

Modified: llvm/trunk/test/MC/X86/x86-64.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-64.s?rev=308818&r1=308817&r2=308818&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86-64.s (original)
+++ llvm/trunk/test/MC/X86/x86-64.s Fri Jul 21 18:30:53 2017
@@ -1509,3 +1509,11 @@ vmovq %xmm0, %rax
 // CHECK: 	movl %r15d, (%r15,%r15)
 // CHECK:  encoding: [0x47,0x89,0x3c,0x3f]
 movl %r15d, (%r15,%r15)
+
+// CHECK: nopq	3735928559(%rbx,%rcx,8)
+// CHECK:  encoding: [0x48,0x0f,0x1f,0x84,0xcb,0xef,0xbe,0xad,0xde]
+nopq	0xdeadbeef(%rbx,%rcx,8)
+
+// CHECK: nopq	%rax
+// CHECK:  encoding: [0x48,0x0f,0x1f,0xc0]
+nopq	%rax