[PATCH] D35568: [AArch64] Use 16 bytes as preferred function alignment on Cortex-A53.

Renato Golin via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Jul 21 16:32:16 PDT 2017

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rengolin added a comment.

So, it seems it was sphinx, but that was loop alignment, 4 bytes on A53, 8 bytes on A57, to do with the fetch alignment. Maybe this is a related issue. Why 16, though?


https://reviews.llvm.org/D35568

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