[PATCH] D35299: [AArch64] Tie source and destination operands for AESMC/AESIMC.

[Florian Hahn via Phabricator via llvm-commits]

fhahn updated this revision to Diff 107705.
fhahn edited the summary of this revision.
fhahn added a comment.

In https://reviews.llvm.org/D35299#816711, @t.p.northover wrote:

> > I'm afraid that it would create problems for the assembler too, wouldn't it?
>
> Yeah, the original causes failures in test/MC. I wonder why that wasn't spotted earlier?


I'm not entirely sure what you mean here. I've updated one of the AArch64 MC tests to build with +fuse-aes, to make sure the constraint does not mess up MC codegen.

> Anyway, I'm not sure the "single-use" heuristic is actually what we should care about. As far as I understand AES these instructions are only ever going to be seen with single-uses in reality so optimizing for other cases is probably premature.
> 
> For out-of-order non-fused implementations the register shouldn't matter as far as I can see, which leaves in-order unfused implementations. I've got much less experience there, but don't they tend to have early forwarding to dependent instructions anyway?
> 
> So perhaps a hybrid approach where the Pattern always picks these pseudo-instructions would be best?

Yes, the single-use case is what we should see in practice. I've removed the single use pattern from the patch.


https://reviews.llvm.org/D35299

Files:
  lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
  lib/Target/AArch64/AArch64InstrInfo.td
  lib/Target/AArch64/AArch64MacroFusion.cpp
  test/CodeGen/AArch64/misched-fusion-aes.ll
  test/MC/AArch64/arm64-crypto.s

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D35299.107705.patch
Type: text/x-patch
Size: 12682 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20170721/6bed9fe6/attachment.bin>