[PATCH] D35635: Optimize {s,u}{add,sub}.with.overflow on ARM
Joel Galenson via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 19 11:27:14 PDT 2017
jgalenson added inline comments.
================
Comment at: lib/Target/ARM/ARMISelLowering.cpp:4484
+ };
+ if (LHS.getOpcode() == ISD::AND &&
+ (isOneConstant(RHS) || isNullConstant(RHS)) &&
----------------
efriedma wrote:
> We should be able to optimize away the AND here using known bits; does that not happen on trunk?
It doesn't because ARM doesn't call setBooleanContents. If there's a way to set that correctly, it would indeed be better. Do you think we could do that?
================
Comment at: test/CodeGen/ARM/su_addsub_overflow.ll:20
+ ; CHECK-NOT: mov
+ ; CHECK: movvc
+}
----------------
efriedma wrote:
> These CHECK lines are not very good; try generating checks with utils/update_llc_test_checks.py. Also, please commit this first and rebase your patch on top of it; that makes it easy to see what happens to the generated code.
That tool does make the changes to the testfiles more obvious, but it also generates overly-specific testcases that seem more brittle. I'll see if I can make a nice middle-ground and update it in a bit.
https://reviews.llvm.org/D35635
More information about the llvm-commits
mailing list