[PATCH] D35635: Optimize {s,u}{add,sub}.with.overflow on ARM

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

Please include full context when you upload patches to Phabricator; see http://llvm.org/docs/Phabricator.html#requesting-a-review-via-the-web-interface.

This sort of overlaps with https://reviews.llvm.org/D35192.



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Comment at: lib/Target/ARM/ARMISelLowering.cpp:4484
+  };
+  if (LHS.getOpcode() == ISD::AND &&
+      (isOneConstant(RHS) || isNullConstant(RHS)) &&
----------------
We should be able to optimize away the AND here using known bits; does that not happen on trunk?


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Comment at: test/CodeGen/ARM/su_addsub_overflow.ll:20
+  ; CHECK-NOT: mov
+  ; CHECK: movvc
+}
----------------
These CHECK lines are not very good; try generating checks with utils/update_llc_test_checks.py.  Also, please commit this first and rebase your patch on top of it; that makes it easy to see what happens to the generated code.


https://reviews.llvm.org/D35635