[PATCH] D33518: [AArch64] Fix stores of zero values

[Geoff Berry via Phabricator via llvm-commits]

gberry added a comment.

I noticed a few code size regressions looking through the diffs of generated code for this change which were caused by:

- the offsets of the stores not having the right alignment to allow for stp x opcodes to be formed
- the offsets of the stores being too large for stp x, but not too large for stp q
- the offsets of the stores being so large that adds are needed to compute the address for str x, but not so large that adds are needed to compute the address for str q



================
Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:9331
+      for (SDValue &OtherAddr : STAddrs) {
+        auto OtherAddrDecomp = BaseIndexOffset::match(OtherAddr, DAG);
+        int64_t Offset = 0;
----------------
Would it not be better to store the BaseIndexOffset in STAddrs instead of re-computing it for every iteration of the StVal->uses() loop?

Also, do you have a use case/benchmark where this helps performance/code size significantly to justify the n^2 checking here?


https://reviews.llvm.org/D33518