[PATCH] D35307: [AArch64] Initial SVE register definitions

[Renato Golin via Phabricator via llvm-commits]

rengolin added a comment.

Hi Amara,

This seems a very raw change, without any further description, comments or proper usage, other than a few changes on random places.

You have to describe what the changes are meant to do, where the documents are (as a refresher), which chapters of the documents those registers are described, and hopefully some use of them somewhere.

Is it not possible to write tests for them? If so, why not?

Is this the first of a series? If yes, there what's the rest? A description of the changes would help, but much better if you pointer to more reviews in the series.

cheers,
--renato



================
Comment at: lib/Target/AArch64/AArch64RegisterInfo.td:33
   def subo64 : SubRegIndex<64>;
+  def qhisub : SubRegIndex<64>;
+  def qsub : SubRegIndex<64>;
----------------
Avoid unnecessary line moves.


================
Comment at: lib/Target/AArch64/AArch64RegisterInfo.td:134
+
+// Purely virtual Vector Granule (VG) Dwarf register
+def VG : AArch64Reg<0, "vg">, DwarfRegNum<[46]>;
----------------
What's this? The "register" that stores the current length of the vectors?


Repository:
  rL LLVM

https://reviews.llvm.org/D35307