[PATCH] D35019: [X86][SandyBridgel] Updating all scheduling information on each SNB instruction about latency, number of uOps and used ports

[Zvi Rackover via Phabricator via llvm-commits]

zvi added inline comments.


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Comment at: lib/Target/X86/X86SchedSandyBridge.td:264
+// HADD, HSUB PS/PD
+// x,x / v,v,v.
+def : WriteRes<WriteFHAdd, [SBPort1]> {
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To minimize the change in this patch, can you please move this block in a separate commit and then rebase this patch?


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Comment at: test/CodeGen/X86/gather-addresses.ll:3
 ; RUN: llc -mtriple=x86_64-win32 -mcpu=nehalem < %s | FileCheck %s --check-prefix=WIN
-; RUN: llc -mtriple=i686-win32 -mcpu=nehalem < %s | FileCheck %s --check-prefix=LIN32
+; RUN: llc -mtriple=i686-win32 -mcpu=nehalem < %s | FileCheck %s --check-prefix=WIN32
 ; rdar://7398554
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Is this change intentional?


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Comment at: test/CodeGen/X86/gather-addresses.ll:19
 ; LIN: sarq    $32, %r[[REG4]]
-; LIN: movsd	(%rdi,%r[[REG1]],8), %xmm0
-; LIN: movhpd	(%rdi,%r[[REG2]],8), %xmm0
-; LIN: movsd	(%rdi,%r[[REG3]],8), %xmm1
-; LIN: movhpd	(%rdi,%r[[REG4]],8), %xmm1
+; LIN: movsd    (%rdi,%rsi,8), %xmm1 # xmm1 = mem[0],zero 
+; LIN: movhpd   (%rdi,%rax,8), %xmm1 # xmm1 = xmm1[0],mem[0] 
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Please keep this file consistent by either preserving the regex checks or converting this file to be update-checks style, but don't mix the two. If you choose the latter, it should be done in a separate patch.


Repository:
  rL LLVM

https://reviews.llvm.org/D35019