[PATCH] D35019: [X86][SandyBridgel] Updating all scheduling information on each SNB instruction about latency, number of uOps and used ports

[Gadi Haber via Phabricator via llvm-commits]

gadi.haber created this revision.

This patch completely replaces the scheduling information for the SandyBridge architecture target by completely modifying the file: X86SchedSandyBridge.td located under the X86 Target.
The SandyBridge architects have provided us with a more accurate information about each instruction latency, num of uOPs and used ports and I use it to replace the existing estimated SNB instructions scheduling and to add missing instructions's information.

**Please note that the patch extensively affects the X86 MC instr scheduling for SNB.**

Also note that this patch will be followed by additional patches for the remaining target architectures HSW, IVB, BDW, SKL and SKX.

The updated and extended information about each instruction includes the following details:
•static latency of the instruction
•number of uOps from which the instruction consists of
•all ports used by the instruction's' uOPs

For example, the following code dictates that instructions, ADC64mr, ADC8mr, SBB64mr, SBB8mr have a static latency of 9 cycles. Each of these instructions is decoded into 6 micro operations which use ports 4, ports 2 or 3 and port 0 and ports 0 or 1 or 5:

def SBWriteResGroup94 : SchedWriteRes<[SBPort4,SBPort23,SBPort0,SBPort015]> {
let Latency = 9;
let NumMicroOps = 6;
let ResourceCycles = [1,2,2,1];

}
 def: InstRW<[SBWriteResGroup94], (instregex "ADC64mr")>;
 def: InstRW<[SBWriteResGroup94], (instregex "ADC8mr")>;
 def: InstRW<[SBWriteResGroup94], (instregex "SBB64mr")>;
 def: InstRW<[SBWriteResGroup94], (instregex "SBB8mr")>;

Note that from header most of the X86SchedSandyBridge.td file was generated by a script.


Repository:
  rL LLVM

https://reviews.llvm.org/D35019

Files:
  lib/Target/X86/X86SchedSandyBridge.td
  test/CodeGen/X86/avx-schedule.ll
  test/CodeGen/X86/bitcast-and-setcc-256.ll
  test/CodeGen/X86/extractelement-legalization-store-ordering.ll
  test/CodeGen/X86/fp128-i128.ll
  test/CodeGen/X86/gather-addresses.ll
  test/CodeGen/X86/illegal-bitfield-loadstore.ll
  test/CodeGen/X86/recip-fastmath.ll
  test/CodeGen/X86/recip-fastmath2.ll
  test/CodeGen/X86/sse-schedule.ll
  test/CodeGen/X86/sse2-schedule.ll
  test/CodeGen/X86/sse3-schedule.ll
  test/CodeGen/X86/sse41-schedule.ll
  test/CodeGen/X86/sse42-schedule.ll
  test/CodeGen/X86/ssse3-schedule.ll

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