[PATCH] D34652: [x86] add SBB optimization for SETAE (uge) condition code

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a comment.

Ping.

According to Agner's latest docs:
http://www.agner.org/optimize/microarchitecture.pdf

All recent AMD uarch *do* recognize sbb with the same operands as an idiom. See Chapters 18/19/20:
"The following instructions are recognized as independent of the input when both operands are the same register:
XOR, SUB, SBB (depends on carry flag only)..."

That would further the case that we want a later pass to insert the xor based on CPU model. Adding those as part of isel would just be code bloat for AMD.


https://reviews.llvm.org/D34652