[PATCH] D34652: [x86] add SBB optimization for SETAE (uge) condition code

[Sanjay Patel via Phabricator via llvm-commits]

spatel added inline comments.


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Comment at: test/CodeGen/X86/sbb.ll:149
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    cmpl %esi, %edi
+; CHECK-NEXT:    sbbl %eax, %eax
----------------
zvi wrote:
> zvi wrote:
> > AFAIK, the processor does avoid false-dependency stalls for the case 'sbb EAX EAX' (unlike xor's and sub's).
> > So we may want to ensure a 'xor EAX EAX' is placed before.
> Typo fix: the processor does **not** avoid false-dependency stalls for the case 'sbb EAX EAX'
Yes, I think that might be a concern. I took a quick look at this, but it's not a small fix from what I can tell:
1. We can't put the xor in the tablegen pat/def because we can't interfere with the EFLAGS result coming from the cmp (the xor must occur before the cmp).
2. We can't use the existing hasUndefRegUpdate() as-is because it's specifically checking operand 1 (and I'm not sure if it would account for #1 either).

The xor for the setcc code is produced by the x86-fixup-setcc pass. We'd probably need to graft into that or create another similar pass?


https://reviews.llvm.org/D34652