[PATCH] D34423: Create TD nodes for ADDCARRY and SUBCARRY opcodes

Stanislav Mekhanoshin via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Jun 21 14:21:40 PDT 2017


rampitec added inline comments.


================
Comment at: include/llvm/Target/TargetSelectionDAG.td:161
+def SDTCarryOp : SDTypeProfile<2, 3, [      // addcarry, subcarry
+  SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisInt<0>, SDTCisVT<1, i1>, SDTCisVT<4, i1>
+]>;
----------------
arsenm wrote:
> rampitec wrote:
> > arsenm wrote:
> > > arsenm wrote:
> > > > i1 is wrong here since it will presumably be legalized to the target's boolean contents at some point, which won't necessarily be i1.
> > > They probably just need to be constrained to int and the same, there's no way to constrain to the TLI hook reported types
> > Isn't bool always i1 regardless of its target representation?
> No, this will be legalized to the target's boolean type. i1 isn't required to be legal for the target. i1 is only used before legalization
OK, if I do not specify exact VT for the carry, then this pattern does not work any longer:


```
def : Pat<
    (addcarry i32:$src0, i32:$src1, i1:$src2),
    (V_ADDC_U32_e64 $src0, $src1, $src2)
>;

```

Since I cannot get that pattern to work there is no use of the new nodes, so I'm about to abandon the proposal.


Repository:
  rL LLVM

https://reviews.llvm.org/D34423





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