[llvm] r305472 - [X86][AVX2] Fix issue in lowerV8I16GeneralSingleInputVectorShuffle that was assuming v8i16 vectors

[Simon Pilgrim via llvm-commits]

Mainly due to the lambda’s captures being a mess, meaning that its a lot easier to reuse V instead of exposing VT.

> On 15 Jun 2017, at 16:40, Craig Topper <craig.topper at gmail.com> wrote:
> 
> Any reason we can't use the VT variable being passed into the function?
> 
> ~Craig
> 
> On Thu, Jun 15, 2017 at 7:52 AM, Simon Pilgrim via llvm-commits <llvm-commits at lists.llvm.org <mailto:llvm-commits at lists.llvm.org>> wrote:
> Author: rksimon
> Date: Thu Jun 15 09:52:30 2017
> New Revision: 305472
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=305472&view=rev <http://llvm.org/viewvc/llvm-project?rev=305472&view=rev>
> Log:
> [X86][AVX2] Fix issue in lowerV8I16GeneralSingleInputVectorShuffle that was assuming v8i16 vectors
> 
> We can use this with v16i16/v32i16 as well.
> 
> Found during fuzz testing.
> 
> Modified:
>     llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>     llvm/trunk/test/CodeGen/X86/vector-shuffle-256-v16.ll
> 
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=305472&r1=305471&r2=305472&view=diff <http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=305472&r1=305471&r2=305472&view=diff>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Jun 15 09:52:30 2017
> @@ -10889,9 +10889,10 @@ static SDValue lowerV8I16GeneralSingleIn
>                   "We need to be changing the number of flipped inputs!");
>            int PSHUFHalfMask[] = {0, 1, 2, 3};
>            std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
> -          V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
> -                          MVT::v8i16, V,
> -                          getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
> +          V = DAG.getNode(
> +              FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
> +              MVT::getVectorVT(MVT::i16, V.getValueSizeInBits() / 16), V,
> +              getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
> 
>            for (int &M : Mask)
>              if (M >= 0 && M == FixIdx)
> 
> Modified: llvm/trunk/test/CodeGen/X86/vector-shuffle-256-v16.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-shuffle-256-v16.ll?rev=305472&r1=305471&r2=305472&view=diff <http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-shuffle-256-v16.ll?rev=305472&r1=305471&r2=305472&view=diff>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/vector-shuffle-256-v16.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/vector-shuffle-256-v16.ll Thu Jun 15 09:52:30 2017
> @@ -1559,6 +1559,24 @@ define <16 x i16> @shuffle_v16i16_17_18_
>    ret <16 x i16> %shuffle
>  }
> 
> +define <16 x i16> @shuffle_v16i16_06_07_01_02_07_00_04_05_14_15_09_10_15_08_12_13(<16 x i16> %a) {
> +; AVX1-LABEL: shuffle_v16i16_06_07_01_02_07_00_04_05_14_15_09_10_15_08_12_13:
> +; AVX1:       # BB#0:
> +; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
> +; AVX1-NEXT:    vmovdqa {{.*#+}} xmm2 = [12,13,14,15,2,3,4,5,14,15,0,1,8,9,10,11]
> +; AVX1-NEXT:    vpshufb %xmm2, %xmm1, %xmm1
> +; AVX1-NEXT:    vpshufb %xmm2, %xmm0, %xmm0
> +; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
> +; AVX1-NEXT:    retq
> +;
> +; AVX2OR512VL-LABEL: shuffle_v16i16_06_07_01_02_07_00_04_05_14_15_09_10_15_08_12_13:
> +; AVX2OR512VL:       # BB#0:
> +; AVX2OR512VL-NEXT:    vpshufb {{.*#+}} ymm0 = ymm0[12,13,14,15,2,3,4,5,14,15,0,1,8,9,10,11,28,29,30,31,18,19,20,21,30,31,16,17,24,25,26,27]
> +; AVX2OR512VL-NEXT:    retq
> +  %1 = shufflevector <16 x i16> %a, <16 x i16> undef, <16 x i32> <i32 6, i32 7, i32 1, i32 2, i32 7, i32 0, i32 4, i32 5, i32 14, i32 15, i32 9, i32 10, i32 15, i32 8, i32 12, i32 13>
> +  ret <16 x i16> %1
> +}
> +
>  ;
>  ; Shuffle to logical bit shifts
>  ;
> 
> 
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