<html><head><meta http-equiv="Content-Type" content="text/html charset=utf-8"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;" class="">Mainly due to the lambda’s captures being a mess, meaning that its a lot easier to reuse V instead of exposing VT.<div class=""><br class=""><div><blockquote type="cite" class=""><div class="">On 15 Jun 2017, at 16:40, Craig Topper <<a href="mailto:craig.topper@gmail.com" class="">craig.topper@gmail.com</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div dir="ltr" class="">Any reason we can't use the VT variable being passed into the function?</div><div class="gmail_extra"><br clear="all" class=""><div class=""><div class="gmail_signature" data-smartmail="gmail_signature">~Craig</div></div>
<br class=""><div class="gmail_quote">On Thu, Jun 15, 2017 at 7:52 AM, Simon Pilgrim via llvm-commits <span dir="ltr" class=""><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank" class="">llvm-commits@lists.llvm.org</a>></span> wrote:<br class=""><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: rksimon<br class="">
Date: Thu Jun 15 09:52:30 2017<br class="">
New Revision: 305472<br class="">
<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=305472&view=rev" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-<wbr class="">project?rev=305472&view=rev</a><br class="">
Log:<br class="">
[X86][AVX2] Fix issue in lowerV8I16GeneralSingleInputVe<wbr class="">ctorShuffle that was assuming v8i16 vectors<br class="">
<br class="">
We can use this with v16i16/v32i16 as well.<br class="">
<br class="">
Found during fuzz testing.<br class="">
<br class="">
Modified:<br class="">
llvm/trunk/lib/Target/X86/<wbr class="">X86ISelLowering.cpp<br class="">
llvm/trunk/test/CodeGen/X86/<wbr class="">vector-shuffle-256-v16.ll<br class="">
<br class="">
Modified: llvm/trunk/lib/Target/X86/<wbr class="">X86ISelLowering.cpp<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=305472&r1=305471&r2=305472&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/lib/Target/<wbr class="">X86/X86ISelLowering.cpp?rev=<wbr class="">305472&r1=305471&r2=305472&<wbr class="">view=diff</a><br class="">
==============================<wbr class="">==============================<wbr class="">==================<br class="">
--- llvm/trunk/lib/Target/X86/<wbr class="">X86ISelLowering.cpp (original)<br class="">
+++ llvm/trunk/lib/Target/X86/<wbr class="">X86ISelLowering.cpp Thu Jun 15 09:52:30 2017<br class="">
@@ -10889,9 +10889,10 @@ static SDValue lowerV8I16GeneralSingleIn<br class="">
"We need to be changing the number of flipped inputs!");<br class="">
int PSHUFHalfMask[] = {0, 1, 2, 3};<br class="">
std::swap(PSHUFHalfMask[<wbr class="">FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);<br class="">
- V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,<br class="">
- MVT::v8i16, V,<br class="">
- getV4X86ShuffleImm8ForMask(<wbr class="">PSHUFHalfMask, DL, DAG));<br class="">
+ V = DAG.getNode(<br class="">
+ FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,<br class="">
+ MVT::getVectorVT(MVT::i16, V.getValueSizeInBits() / 16), V,<br class="">
+ getV4X86ShuffleImm8ForMask(<wbr class="">PSHUFHalfMask, DL, DAG));<br class="">
<br class="">
for (int &M : Mask)<br class="">
if (M >= 0 && M == FixIdx)<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/X86/<wbr class="">vector-shuffle-256-v16.ll<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-shuffle-256-v16.ll?rev=305472&r1=305471&r2=305472&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/test/<wbr class="">CodeGen/X86/vector-shuffle-<wbr class="">256-v16.ll?rev=305472&r1=<wbr class="">305471&r2=305472&view=diff</a><br class="">
==============================<wbr class="">==============================<wbr class="">==================<br class="">
--- llvm/trunk/test/CodeGen/X86/<wbr class="">vector-shuffle-256-v16.ll (original)<br class="">
+++ llvm/trunk/test/CodeGen/X86/<wbr class="">vector-shuffle-256-v16.ll Thu Jun 15 09:52:30 2017<br class="">
@@ -1559,6 +1559,24 @@ define <16 x i16> @shuffle_v16i16_17_18_<br class="">
ret <16 x i16> %shuffle<br class="">
}<br class="">
<br class="">
+define <16 x i16> @shuffle_v16i16_06_07_01_02_<wbr class="">07_00_04_05_14_15_09_10_15_08_<wbr class="">12_13(<16 x i16> %a) {<br class="">
+; AVX1-LABEL: shuffle_v16i16_06_07_01_02_07_<wbr class="">00_04_05_14_15_09_10_15_08_12_<wbr class="">13:<br class="">
+; AVX1: # BB#0:<br class="">
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1<br class="">
+; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [12,13,14,15,2,3,4,5,14,15,0,<wbr class="">1,8,9,10,11]<br class="">
+; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1<br class="">
+; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0<br class="">
+; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0<br class="">
+; AVX1-NEXT: retq<br class="">
+;<br class="">
+; AVX2OR512VL-LABEL: shuffle_v16i16_06_07_01_02_07_<wbr class="">00_04_05_14_15_09_10_15_08_12_<wbr class="">13:<br class="">
+; AVX2OR512VL: # BB#0:<br class="">
+; AVX2OR512VL-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[12,13,14,15,2,3,4,5,14,<wbr class="">15,0,1,8,9,10,11,28,29,30,31,<wbr class="">18,19,20,21,30,31,16,17,24,25,<wbr class="">26,27]<br class="">
+; AVX2OR512VL-NEXT: retq<br class="">
+ %1 = shufflevector <16 x i16> %a, <16 x i16> undef, <16 x i32> <i32 6, i32 7, i32 1, i32 2, i32 7, i32 0, i32 4, i32 5, i32 14, i32 15, i32 9, i32 10, i32 15, i32 8, i32 12, i32 13><br class="">
+ ret <16 x i16> %1<br class="">
+}<br class="">
+<br class="">
;<br class="">
; Shuffle to logical bit shifts<br class="">
;<br class="">
<br class="">
<br class="">
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