[PATCH] D33099: AMD Jaguar scheduler doesn't correctly model 256-bit AVX instructions

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

I really don't understand why you are having to change the throughput calculation as part of this - split this as another patch?



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Comment at: lib/Target/X86/X86ScheduleBtVer2.td:350
+}
+def : InstRW<[WriteFAddYY], (instregex "VADD(SUB)?P(S|D)Yrr", "VSUBP(S|D)Yrr")>;
+
----------------
Why WriteFAddYY not WriteFAddY ?


================
Comment at: lib/Target/X86/X86ScheduleBtVer2.td:356
+}
+def : InstRW<[WriteFAddYMLd, ReadAfterLd], (instregex "VADD(SUB)?P(S|D)Yrm", "VSUBP(S|D)Yrm")>;
+
----------------
WriteFAddYLd ?


================
Comment at: lib/Target/X86/X86ScheduleBtVer2.td:362
+}
+def : InstRW<[WriteVDIV], (instregex "VDIVP(D|S)Yrr")>;
+
----------------
WriteFDivY?


https://reviews.llvm.org/D33099