[PATCH] D33650: MachineVerifier: Verify liveins list

Matthias Braun via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue May 30 12:53:21 PDT 2017 

MatzeB added a comment.

In https://reviews.llvm.org/D33650#767962, @kparzysz wrote:

> I don't think we should be aborting on legal code.  Maybe we should add an option to treat all verifier reports as warnings (i.e. continue the compilation even if issues were reported)?


Well looking at the existing situation with targets, we probably have to keep the pristine/reserved checks separate. Just looking at the liveness check currently fails a bunch of lit tests for me:

  LLVM :: CodeGen/ARM/2010-05-18-LocalAllocCrash.ll
  LLVM :: CodeGen/ARM/2011-04-12-FastRegAlloc.ll
  LLVM :: CodeGen/ARM/2011-05-04-MultipleLandingPadSuccs.ll
  LLVM :: CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll
  LLVM :: CodeGen/ARM/ARMLoadStoreDBG.mir
  LLVM :: CodeGen/ARM/Windows/dbzchk.ll
  LLVM :: CodeGen/ARM/Windows/no-aeabi.ll
  LLVM :: CodeGen/ARM/atomic-cmpxchg.ll
  LLVM :: CodeGen/ARM/atomic-load-store.ll
  LLVM :: CodeGen/ARM/atomic-op.ll
  LLVM :: CodeGen/ARM/atomic-ops-v8.ll
  LLVM :: CodeGen/ARM/cmpxchg-O0.ll
  LLVM :: CodeGen/ARM/coalesce-dbgvalue.ll
  LLVM :: CodeGen/ARM/coalesce-subregs.ll
  LLVM :: CodeGen/ARM/copy-paired-reg.ll
  LLVM :: CodeGen/ARM/crash-greedy.ll
  LLVM :: CodeGen/ARM/domain-conv-vmovs.ll
  LLVM :: CodeGen/ARM/fast-isel-br-const.ll
  LLVM :: CodeGen/ARM/fast-isel-br-phi.ll
  LLVM :: CodeGen/ARM/fast-isel-call-multi-reg-return.ll
  LLVM :: CodeGen/ARM/fast-isel-call.ll
  LLVM :: CodeGen/ARM/fast-isel-cmp-imm.ll
  LLVM :: CodeGen/ARM/fast-isel-conversion.ll
  LLVM :: CodeGen/ARM/fast-isel-crash.ll
  LLVM :: CodeGen/ARM/fast-isel-deadcode.ll
  LLVM :: CodeGen/ARM/fast-isel-fold.ll
  LLVM :: CodeGen/ARM/fast-isel-frameaddr.ll
  LLVM :: CodeGen/ARM/fast-isel-intrinsic.ll
  LLVM :: CodeGen/ARM/fast-isel-mvn.ll
  LLVM :: CodeGen/ARM/fast-isel-pred.ll
  LLVM :: CodeGen/ARM/fast-isel-static.ll
  LLVM :: CodeGen/ARM/fast-isel-update-valuemap-for-extract.ll
  LLVM :: CodeGen/ARM/fast-isel-vaddd.ll
  LLVM :: CodeGen/ARM/fast-isel-vararg.ll
  LLVM :: CodeGen/ARM/fast-isel.ll
  LLVM :: CodeGen/ARM/func-argpassing-endian.ll
  LLVM :: CodeGen/ARM/gpr-paired-spill.ll
  LLVM :: CodeGen/ARM/ifconv-kills.ll
  LLVM :: CodeGen/ARM/ifcvt-dead-def.ll
  LLVM :: CodeGen/ARM/inlineasm-64bit.ll
  LLVM :: CodeGen/ARM/ldm-stm-base-materialization.ll
  LLVM :: CodeGen/ARM/ldm-stm-i256.ll
  LLVM :: CodeGen/ARM/ldrd.ll
  LLVM :: CodeGen/ARM/memcpy-ldm-stm.ll
  LLVM :: CodeGen/ARM/neon_spill.ll
  LLVM :: CodeGen/ARM/optselect-regclass.ll
  LLVM :: CodeGen/ARM/pic.ll
  LLVM :: CodeGen/ARM/sched-it-debug-nodes.mir
  LLVM :: CodeGen/ARM/stack-alignment.ll
  LLVM :: CodeGen/ARM/struct_byval_arm_t1_t2.ll
  LLVM :: CodeGen/ARM/swift-return.ll
  LLVM :: CodeGen/ARM/swifterror.ll
  LLVM :: CodeGen/ARM/swiftself.ll
  LLVM :: CodeGen/ARM/tail-dup-kill-flags.ll
  LLVM :: CodeGen/ARM/thumb-big-stack.ll
  LLVM :: CodeGen/ARM/urem-opt-size.ll
  LLVM :: CodeGen/Hexagon/ifcvt-live-subreg.mir
  LLVM :: CodeGen/Hexagon/livephysregs-lane-masks.mir
  LLVM :: CodeGen/Hexagon/livephysregs-lane-masks2.mir
  LLVM :: CodeGen/MIR/ARM/cfi-same-value.mir
  LLVM :: CodeGen/PowerPC/2006-11-10-DAGCombineMiscompile.ll
  LLVM :: CodeGen/PowerPC/2006-12-07-SelectCrash.ll
  LLVM :: CodeGen/PowerPC/2008-03-17-RegScavengerCrash.ll
  LLVM :: CodeGen/PowerPC/2008-06-23-LiveVariablesCrash.ll
  LLVM :: CodeGen/PowerPC/2008-10-28-f128-i32.ll
  LLVM :: CodeGen/PowerPC/2011-12-06-SpillAndRestoreCR.ll
  LLVM :: CodeGen/PowerPC/2012-09-16-TOC-entry-check.ll
  LLVM :: CodeGen/PowerPC/crbit-asm.ll
  LLVM :: CodeGen/PowerPC/crbits.ll
  LLVM :: CodeGen/PowerPC/ctrloop-sh.ll
  LLVM :: CodeGen/PowerPC/ctrloops.ll
  LLVM :: CodeGen/PowerPC/expand-contiguous-isel.ll
  LLVM :: CodeGen/PowerPC/expand-isel.ll
  LLVM :: CodeGen/PowerPC/fast-isel-conversion.ll
  LLVM :: CodeGen/PowerPC/float-to-int.ll
  LLVM :: CodeGen/PowerPC/fold-zero.ll
  LLVM :: CodeGen/PowerPC/fp-to-int-to-fp.ll
  LLVM :: CodeGen/PowerPC/i1-ext-fold.ll
  LLVM :: CodeGen/PowerPC/i1-to-double.ll
  LLVM :: CodeGen/PowerPC/i64_fp_round.ll
  LLVM :: CodeGen/PowerPC/ifcvt.ll
  LLVM :: CodeGen/PowerPC/int-fp-conv-1.ll
  LLVM :: CodeGen/PowerPC/isel.ll
  LLVM :: CodeGen/PowerPC/mul-with-overflow.ll
  LLVM :: CodeGen/PowerPC/optcmp.ll
  LLVM :: CodeGen/PowerPC/p8-isel-sched.ll
  LLVM :: CodeGen/PowerPC/ppc-crbits-onoff.ll
  LLVM :: CodeGen/PowerPC/ppc32-lshrti3.ll
  LLVM :: CodeGen/PowerPC/ppc64-32bit-addic.ll
  LLVM :: CodeGen/PowerPC/ppc64-toc.ll
  LLVM :: CodeGen/PowerPC/ppcf128sf.ll
  LLVM :: CodeGen/PowerPC/pristine-and-livein.mir
  LLVM :: CodeGen/PowerPC/select-i1-vs-i1.ll
  LLVM :: CodeGen/PowerPC/select_const.ll
  LLVM :: CodeGen/PowerPC/subreg-postra.ll
  LLVM :: CodeGen/Thumb/2009-08-20-ISelBug.ll
  LLVM :: CodeGen/Thumb/2014-06-10-thumb1-ldst-opt-bug.ll
  LLVM :: CodeGen/Thumb/and_neg.ll
  LLVM :: CodeGen/Thumb/ldm-merge-call.ll
  LLVM :: CodeGen/Thumb/ldm-stm-base-materialization-thumb2.ll
  LLVM :: CodeGen/Thumb/ldm-stm-base-materialization.ll
  LLVM :: CodeGen/Thumb/optionaldef-scheduling.ll
  LLVM :: CodeGen/Thumb/tbb-reuse.mir
  LLVM :: CodeGen/Thumb/thumb-ldm.ll
  LLVM :: CodeGen/Thumb2/constant-islands.ll
  LLVM :: CodeGen/Thumb2/crash.ll
  LLVM :: CodeGen/Thumb2/large-call.ll
  LLVM :: CodeGen/Thumb2/segmented-stacks.ll
  LLVM :: CodeGen/X86/block-placement.mir
  LLVM :: CodeGen/X86/catchret-fallthrough.ll
  LLVM :: CodeGen/X86/crash.ll
  LLVM :: CodeGen/X86/implicit-null-check.ll
  LLVM :: CodeGen/X86/implicit-null-checks.mir
  LLVM :: CodeGen/X86/inline-asm-fpstack.ll
  LLVM :: CodeGen/X86/win-catchpad-csrs.ll
  LLVM :: CodeGen/X86/win-catchpad-nested-cxx.ll
  LLVM :: CodeGen/X86/win-catchpad.ll
  LLVM :: CodeGen/X86/win-cleanuppad.ll

Fixing this will be some effort and will take time. I have fixed aarch64 related checks and will look some more into ARM and X86.

But I think this brings us back to a similar discussion as http://llvm.org/PR32146. I think it may be a good idea to add some hooks so targets can indicate their level of verifier cleanliness. This would be a nice bringup tool that would allow us to enable the machine verifier in expensive checks by default or in this case indicate whether we want the "no pristines and no reserved regs in liveins" rule in the verifier enabled yet.


Repository:
  rL LLVM

https://reviews.llvm.org/D33650

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