[PATCH] D33656: [PowerPC] Correctly specify the cache line size for Power 7, 8 and 9.
Stefan Pintilie via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon May 29 13:01:06 PDT 2017
stefanp created this revision.
The cache line size for Power 7, 8 and 9 is 128 bytes.
Otherwise a default of 64 bytes is assumed.
https://reviews.llvm.org/D33656
Files:
lib/Target/PowerPC/PPCTargetTransformInfo.cpp
test/CodeGen/PowerPC/ppc64-get-cache-line-size.ll
Index: test/CodeGen/PowerPC/ppc64-get-cache-line-size.ll
===================================================================
--- /dev/null
+++ test/CodeGen/PowerPC/ppc64-get-cache-line-size.ll
@@ -0,0 +1,53 @@
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-ppc-prefetching=true | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-ppc-prefetching=true -ppc-loop-prefetch-cache-line=64 | FileCheck %s -check-prefix=CHECK-DCBT
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -enable-ppc-prefetching=true | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -enable-ppc-prefetching=true -ppc-loop-prefetch-cache-line=64 | FileCheck %s -check-prefix=CHECK-DCBT
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -enable-ppc-prefetching=true | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -enable-ppc-prefetching=true -ppc-loop-prefetch-cache-line=64 | FileCheck %s -check-prefix=CHECK-DCBT
+; RUN: llc < %s -march=ppc64 -mcpu=a2 -enable-ppc-prefetching=true | FileCheck %s -check-prefix=CHECK-DCBT
+
+; Function Attrs: nounwind
+define signext i32 @main() {
+entry:
+ %call = tail call double* bitcast (double* (...)* @magicf to double* ()*)()
+ %call115 = tail call signext i32 bitcast (i32 (...)* @magici to i32 ()*)()
+ %cmp16 = icmp sgt i32 %call115, 0
+ br i1 %cmp16, label %for.body, label %for.cond.cleanup
+
+for.cond.cleanup.loopexit: ; preds = %for.body
+ %phitmp = fptosi double %add5 to i32
+ br label %for.cond.cleanup
+
+for.cond.cleanup: ; preds = %for.cond.cleanup.loopexit, %entry
+ %res.0.lcssa = phi i32 [ 0, %entry ], [ %phitmp, %for.cond.cleanup.loopexit ]
+ ret i32 %res.0.lcssa
+
+for.body: ; preds = %entry, %for.body
+ %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
+ %res.017 = phi double [ %add5, %for.body ], [ 0.000000e+00, %entry ]
+ %arrayidx = getelementptr inbounds double, double* %call, i64 %indvars.iv
+ %0 = load double, double* %arrayidx, align 8
+ %add = fadd double %res.017, %0
+ %1 = add nuw nsw i64 %indvars.iv, 8
+ %arrayidx4 = getelementptr inbounds double, double* %call, i64 %1
+ %2 = load double, double* %arrayidx4, align 8
+ %add5 = fadd double %add, %2
+ %indvars.iv.next = add nuw i64 %indvars.iv, 1
+ %call1 = tail call signext i32 bitcast (i32 (...)* @magici to i32 ()*)()
+ %3 = sext i32 %call1 to i64
+ %cmp = icmp slt i64 %indvars.iv.next, %3
+ br i1 %cmp, label %for.body, label %for.cond.cleanup.loopexit
+; CHECK: main
+; CHECK: dcbt
+; CHECK-NOT: dcbt
+; CHECK: blr
+; CHECK-DCBT: main
+; CHECK-DCBT: dcbt
+; CHECK-DCBT: dcbt
+; CHECK-DCBT: blr
+}
+
+declare double* @magicf(...)
+
+declare signext i32 @magici(...)
+
Index: lib/Target/PowerPC/PPCTargetTransformInfo.cpp
===================================================================
--- lib/Target/PowerPC/PPCTargetTransformInfo.cpp
+++ lib/Target/PowerPC/PPCTargetTransformInfo.cpp
@@ -239,9 +239,18 @@
}
unsigned PPCTTIImpl::getCacheLineSize() {
- // This is currently only used for the data prefetch pass which is only
- // enabled for BG/Q by default.
- return CacheLineSize;
+ // Check first if the user specified a custom line size.
+ if (CacheLineSize.getNumOccurrences() > 0)
+ return CacheLineSize;
+
+ // On P7, P8 or P9 we have a cache line size of 128.
+ unsigned Directive = ST->getDarwinDirective();
+ if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 ||
+ Directive == PPC::DIR_PWR9)
+ return 128;
+
+ // On other processors return a default of 64 bytes.
+ return 64;
}
unsigned PPCTTIImpl::getPrefetchDistance() {
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