[PATCH] D33455: [AMDGPU] Combine and (srl) into shl (bfe)

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: lib/Target/AMDGPU/AMDGPUISelLowering.cpp:3482
+    if ((OffsetVal + WidthVal) >= 32 &&
+        !(Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS &&
+          OffsetVal == 16 && WidthVal == 16)) {
----------------
There is an SDWA subtarget feature


================
Comment at: lib/Target/AMDGPU/SIISelLowering.cpp:4242
+    // nb = number of trailing zeroes in mask
+    // It can be optimized out using SDWA for GFX8+ in the finalizer,
+    // given that we are selecting 8 or 16 bit fields starting at byte boundary.
----------------
s/finalizer/SDWA pass/


================
Comment at: test/CodeGen/AMDGPU/bfe-combine.ll:3
+
+; CHECK-LABEL: {{^}}bfe_combine8:
+; CHECK: v_bfe_u32 v[[BFE:[0-9]+]], v{{[0-9]+}}, 8, 8
----------------
s/CHECK/GCN


Repository:
  rL LLVM

https://reviews.llvm.org/D33455