[PATCH] D32763: [PPC] Lower load acquire/seq_cst trailing fence to cmp + bne + isync.

[Kit Barton via Phabricator via llvm-commits]

kbarton accepted this revision.
kbarton added a comment.
This revision is now accepted and ready to land.

LGTM.
Thanks for adding the additional test case!



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Comment at: llvm/lib/Target/PowerPC/PPCInstr64Bit.td:967
+
+let isBarrier = 1, isPseudo = 1, Defs = [CR7], Itinerary = IIC_LdStSync in
+def CFENCE8 : Pseudo<(outs), (ins g8rc:$cr), "#CFENCE8", []>;
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timshen wrote:
> kbarton wrote:
> > Do we also need to mark Uses = [CR7]?
> I'm not sure - what does Uses exactly mean?
> 
> I didn't add, because a search for "clobbers" in PPCInstr64Bit.td gives me examples that clobbers are added through "Defs" without "Uses".
Yeah, I just verified this with Nemanja. We want to use the Def to mark it as clobbered. The Use of CR7 is internal to this pseudo instruction, but there is no way to indicate that. So if we mark this with an explicit use of CR7, the machinery may try to find the definition of that but won't consider the fact that this instruction is defining it also. 


https://reviews.llvm.org/D32763