[PATCH] D32763: [PPC] Lower load acquire/seq_cst trailing fence to cmp + bne + isync.
Tim Shen via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon May 15 14:41:15 PDT 2017
timshen updated this revision to Diff 99065.
timshen added a comment.
Add a test case for store to an unrelated location after load.
https://reviews.llvm.org/D32763
Files:
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.h
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/test/CodeGen/PowerPC/atomic-2.ll
llvm/test/CodeGen/PowerPC/atomics-indexed.ll
llvm/test/CodeGen/PowerPC/atomics-regression.ll
llvm/test/CodeGen/PowerPC/atomics.ll
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