[llvm] r303133 - [InstCombine] add tests for PR32791; NFC

Sanjay Patel via llvm-commits llvm-commits at lists.llvm.org
Mon May 15 17:32:20 PDT 2017


This is just documenting the current status. If we choose not to transform
these in InstCombine, then we should have a record of that limitation that
we acknowledge is a good thing. This way someone won't come along in the
future and wonder if the transform doesn't exist intentionally or it's just
an oversight. I can add some test comments once we have a conclusion in
D33172.

On Mon, May 15, 2017 at 6:23 PM, Davide Italiano <davide at freebsd.org> wrote:

> On Mon, May 15, 2017 at 4:59 PM, Sanjay Patel via llvm-commits
> <llvm-commits at lists.llvm.org> wrote:
> > Author: spatel
> > Date: Mon May 15 18:59:28 2017
> > New Revision: 303133
> >
> > URL: http://llvm.org/viewvc/llvm-project?rev=303133&view=rev
> > Log:
> > [InstCombine] add tests for PR32791; NFC
> >
>
> I'm slightly confused by these tests being committed inside
> InstCombine & labeled as InstCombine.
> We seem to not have an agreement yet on whether this transformation
> should live, so I don't see the reason for committing these
> beforehand.
>
> > Modified:
> >     llvm/trunk/test/Transforms/InstCombine/logical-select.ll
> >
> > Modified: llvm/trunk/test/Transforms/InstCombine/logical-select.ll
> > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/
> Transforms/InstCombine/logical-select.ll?rev=303133&
> r1=303132&r2=303133&view=diff
> > ============================================================
> ==================
> > --- llvm/trunk/test/Transforms/InstCombine/logical-select.ll (original)
> > +++ llvm/trunk/test/Transforms/InstCombine/logical-select.ll Mon May 15
> 18:59:28 2017
> > @@ -62,6 +62,76 @@ define i32 @poo(i32 %a, i32 %b, i32 %c,
> >    ret i32 %t3
> >  }
> >
> > +; PR32791 - https://bugs.llvm.org//show_bug.cgi?id=32791
> > +; Fold two selects with inverted predicates and zero operands.
> > +define i32 @fold_inverted_icmp_preds(i32 %a, i32 %b, i32 %c, i32 %d) {
> > +; CHECK-LABEL: @fold_inverted_icmp_preds(
> > +; CHECK-NEXT:    [[CMP1:%.*]] = icmp slt i32 %a, %b
> > +; CHECK-NEXT:    [[SEL1:%.*]] = select i1 [[CMP1]], i32 %c, i32 0
> > +; CHECK-NEXT:    [[CMP2:%.*]] = icmp sge i32 %a, %b
> > +; CHECK-NEXT:    [[SEL2:%.*]] = select i1 [[CMP2]], i32 %d, i32 0
> > +; CHECK-NEXT:    [[OR:%.*]] = or i32 [[SEL1]], [[SEL2]]
> > +; CHECK-NEXT:    ret i32 [[OR]]
> > +;
> > +  %cmp1 = icmp slt i32 %a, %b
> > +  %sel1 = select i1 %cmp1, i32 %c, i32 0
> > +  %cmp2 = icmp sge i32 %a, %b
> > +  %sel2 = select i1 %cmp2, i32 %d, i32 0
> > +  %or = or i32 %sel1, %sel2
> > +  ret i32 %or
> > +}
> > +
> > +define i32 @fold_inverted_icmp_preds_reverse(i32 %a, i32 %b, i32 %c,
> i32 %d) {
> > +; CHECK-LABEL: @fold_inverted_icmp_preds_reverse(
> > +; CHECK-NEXT:    [[CMP1:%.*]] = icmp slt i32 %a, %b
> > +; CHECK-NEXT:    [[SEL1:%.*]] = select i1 [[CMP1]], i32 0, i32 %c
> > +; CHECK-NEXT:    [[CMP2:%.*]] = icmp sge i32 %a, %b
> > +; CHECK-NEXT:    [[SEL2:%.*]] = select i1 [[CMP2]], i32 0, i32 %d
> > +; CHECK-NEXT:    [[OR:%.*]] = or i32 [[SEL1]], [[SEL2]]
> > +; CHECK-NEXT:    ret i32 [[OR]]
> > +;
> > +  %cmp1 = icmp slt i32 %a, %b
> > +  %sel1 = select i1 %cmp1, i32 0, i32 %c
> > +  %cmp2 = icmp sge i32 %a, %b
> > +  %sel2 = select i1 %cmp2, i32 0, i32 %d
> > +  %or = or i32 %sel1, %sel2
> > +  ret i32 %or
> > +}
> > +
> > +define i32 @fold_inverted_fcmp_preds(float %a, float %b, i32 %c, i32
> %d) {
> > +; CHECK-LABEL: @fold_inverted_fcmp_preds(
> > +; CHECK-NEXT:    [[CMP1:%.*]] = fcmp olt float %a, %b
> > +; CHECK-NEXT:    [[SEL1:%.*]] = select i1 [[CMP1]], i32 %c, i32 0
> > +; CHECK-NEXT:    [[CMP2:%.*]] = fcmp uge float %a, %b
> > +; CHECK-NEXT:    [[SEL2:%.*]] = select i1 [[CMP2]], i32 %d, i32 0
> > +; CHECK-NEXT:    [[OR:%.*]] = or i32 [[SEL1]], [[SEL2]]
> > +; CHECK-NEXT:    ret i32 [[OR]]
> > +;
> > +  %cmp1 = fcmp olt float %a, %b
> > +  %sel1 = select i1 %cmp1, i32 %c, i32 0
> > +  %cmp2 = fcmp uge float %a, %b
> > +  %sel2 = select i1 %cmp2, i32 %d, i32 0
> > +  %or = or i32 %sel1, %sel2
> > +  ret i32 %or
> > +}
> > +
> > +define <2 x i32> @fold_inverted_icmp_vector_preds(<2 x i32> %a, <2 x
> i32> %b, <2 x i32> %c, <2 x i32> %d) {
> > +; CHECK-LABEL: @fold_inverted_icmp_vector_preds(
> > +; CHECK-NEXT:    [[CMP1:%.*]] = icmp ne <2 x i32> %a, %b
> > +; CHECK-NEXT:    [[SEL1:%.*]] = select <2 x i1> [[CMP1]], <2 x i32> %c,
> <2 x i32> zeroinitializer
> > +; CHECK-NEXT:    [[CMP2:%.*]] = icmp eq <2 x i32> %a, %b
> > +; CHECK-NEXT:    [[SEL2:%.*]] = select <2 x i1> [[CMP2]], <2 x i32> %d,
> <2 x i32> zeroinitializer
> > +; CHECK-NEXT:    [[OR:%.*]] = or <2 x i32> [[SEL1]], [[SEL2]]
> > +; CHECK-NEXT:    ret <2 x i32> [[OR]]
> > +;
> > +  %cmp1 = icmp ne <2 x i32> %a, %b
> > +  %sel1 = select <2 x i1> %cmp1, <2 x i32> %c, <2 x i32> <i32 0, i32 0>
> > +  %cmp2 = icmp eq <2 x i32> %a, %b
> > +  %sel2 = select <2 x i1> %cmp2, <2 x i32> %d, <2 x i32> <i32 0, i32 0>
> > +  %or = or <2 x i32> %sel1, %sel2
> > +  ret <2 x i32> %or
> > +}
> > +
> >  define i32 @par(i32 %a, i32 %b, i32 %c, i32 %d) {
> >  ; CHECK-LABEL: @par(
> >  ; CHECK-NEXT:    [[T0:%.*]] = icmp slt i32 %a, %b
> >
> >
> > _______________________________________________
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> > llvm-commits at lists.llvm.org
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>
> --
> Davide
>
> "There are no solved problems; there are only problems that are more
> or less solved" -- Henri Poincare
>
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