[PATCH] D33117: [AMDGPU] Cache live-ins and register pressure in scheduler

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec updated this revision to Diff 98836.
rampitec edited the summary of this revision.
rampitec added a comment.

Added second very small cache to reuse calculated live set of a block as its only successor live-in set.
Simplified the loop inside computeBlockPressure() to catch end() of the block without code duplication.
Adjusted initial block iterator to the first instruction of the first (topologically) region to save few iterations in some blocks.
Diff is now created against it parent review https://reviews.llvm.org/D33105 to show only the real changes.


Repository:
  rL LLVM

https://reviews.llvm.org/D33117

Files:
  lib/Target/AMDGPU/GCNSchedStrategy.cpp
  lib/Target/AMDGPU/GCNSchedStrategy.h

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