[llvm] r302644 - [SystemZ] Add translate/convert instructions
Ulrich Weigand via llvm-commits
llvm-commits at lists.llvm.org
Wed May 10 05:41:12 PDT 2017
Author: uweigand
Date: Wed May 10 07:41:12 2017
New Revision: 302644
URL: http://llvm.org/viewvc/llvm-project?rev=302644&view=rev
Log:
[SystemZ] Add translate/convert instructions
This adds the set of character-set translate and convert instructions
for assembler / disassembler use.
Modified:
llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td
llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ13.td
llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ196.td
llvm/trunk/lib/Target/SystemZ/SystemZScheduleZEC12.td
llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt
llvm/trunk/test/MC/SystemZ/insn-bad.s
llvm/trunk/test/MC/SystemZ/insn-good.s
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td?rev=302644&r1=302643&r2=302644&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td Wed May 10 07:41:12 2017
@@ -2355,6 +2355,15 @@ class UnaryRRE<string mnemonic, bits<16>
let OpType = "reg";
}
+class UnaryMemRRFc<string mnemonic, bits<16> opcode,
+ RegisterOperand cls1, RegisterOperand cls2>
+ : InstRRFc<opcode, (outs cls2:$R2, cls1:$R1), (ins cls1:$R1src),
+ mnemonic#"\t$R1, $R2", []> {
+ let Constraints = "$R1 = $R1src";
+ let DisableEncoding = "$R1src";
+ let M3 = 0;
+}
+
class UnaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
RegisterOperand cls, Immediate imm>
: InstRIa<opcode, (outs cls:$R1), (ins imm:$I2),
@@ -2610,6 +2619,15 @@ class SideEffectBinaryMemMemRRE<string m
let DisableEncoding = "$R1src, $R2src";
}
+class SideEffectBinaryMemMemRRFc<string mnemonic, bits<16> opcode,
+ RegisterOperand cls1, RegisterOperand cls2>
+ : InstRRFc<opcode, (outs cls1:$R1, cls2:$R2), (ins cls1:$R1src, cls2:$R2src),
+ mnemonic#"\t$R1, $R2", []> {
+ let Constraints = "$R1 = $R1src, $R2 = $R2src";
+ let DisableEncoding = "$R1src, $R2src";
+ let M3 = 0;
+}
+
class BinaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
RegisterOperand cls1, RegisterOperand cls2>
: InstRR<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
@@ -2674,6 +2692,20 @@ class BinaryRRFb<string mnemonic, bits<1
let M4 = 0;
}
+class BinaryMemRRFc<string mnemonic, bits<16> opcode,
+ RegisterOperand cls1, RegisterOperand cls2, Immediate imm>
+ : InstRRFc<opcode, (outs cls2:$R2, cls1:$R1), (ins cls1:$R1src, imm:$M3),
+ mnemonic#"\t$R1, $R2, $M3", []> {
+ let Constraints = "$R1 = $R1src";
+ let DisableEncoding = "$R1src";
+}
+
+multiclass BinaryMemRRFcOpt<string mnemonic, bits<16> opcode,
+ RegisterOperand cls1, RegisterOperand cls2> {
+ def "" : BinaryMemRRFc<mnemonic, opcode, cls1, cls2, imm32zx4>;
+ def Opt : UnaryMemRRFc<mnemonic, opcode, cls1, cls2>;
+}
+
class BinaryRRFe<string mnemonic, bits<16> opcode, RegisterOperand cls1,
RegisterOperand cls2>
: InstRRFe<opcode, (outs cls1:$R1), (ins imm32zx4:$M3, cls2:$R2),
@@ -3339,6 +3371,23 @@ class SideEffectTernaryRRFc<string mnemo
: InstRRFc<opcode, (outs), (ins cls1:$R1, cls2:$R2, imm:$M3),
mnemonic#"\t$R1, $R2, $M3", []>;
+class SideEffectTernaryMemMemRRFc<string mnemonic, bits<16> opcode,
+ RegisterOperand cls1, RegisterOperand cls2,
+ Immediate imm>
+ : InstRRFc<opcode, (outs cls1:$R1, cls2:$R2),
+ (ins cls1:$R1src, cls2:$R2src, imm:$M3),
+ mnemonic#"\t$R1, $R2, $M3", []> {
+ let Constraints = "$R1 = $R1src, $R2 = $R2src";
+ let DisableEncoding = "$R1src, $R2src";
+}
+
+multiclass SideEffectTernaryMemMemRRFcOpt<string mnemonic, bits<16> opcode,
+ RegisterOperand cls1,
+ RegisterOperand cls2> {
+ def "" : SideEffectTernaryMemMemRRFc<mnemonic, opcode, cls1, cls2, imm32zx4>;
+ def Opt : SideEffectBinaryMemMemRRFc<mnemonic, opcode, cls1, cls2>;
+}
+
class SideEffectTernarySSF<string mnemonic, bits<12> opcode,
RegisterOperand cls>
: InstSSF<opcode, (outs),
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td?rev=302644&r1=302643&r2=302644&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td Wed May 10 07:41:12 2017
@@ -1594,6 +1594,47 @@ let Predicates = [FeatureInterlockedAcce
}
//===----------------------------------------------------------------------===//
+// Translate and convert
+//===----------------------------------------------------------------------===//
+
+let mayLoad = 1, mayStore = 1 in
+ def TR : SideEffectBinarySSa<"tr", 0xDC>;
+
+let mayLoad = 1, Defs = [CC, R0L, R1D] in {
+ def TRT : SideEffectBinarySSa<"trt", 0xDD>;
+ def TRTR : SideEffectBinarySSa<"trtr", 0xD0>;
+}
+
+let mayLoad = 1, mayStore = 1, Uses = [R0L] in
+ def TRE : SideEffectBinaryMemMemRRE<"tre", 0xB2A5, GR128, GR64>;
+
+let mayLoad = 1, Uses = [R1D], Defs = [CC] in {
+ defm TRTE : BinaryMemRRFcOpt<"trte", 0xB9BF, GR128, GR64>;
+ defm TRTRE : BinaryMemRRFcOpt<"trtre", 0xB9BD, GR128, GR64>;
+}
+
+let mayLoad = 1, mayStore = 1, Uses = [R0L, R1D], Defs = [CC] in {
+ defm TROO : SideEffectTernaryMemMemRRFcOpt<"troo", 0xB993, GR128, GR64>;
+ defm TROT : SideEffectTernaryMemMemRRFcOpt<"trot", 0xB992, GR128, GR64>;
+ defm TRTO : SideEffectTernaryMemMemRRFcOpt<"trto", 0xB991, GR128, GR64>;
+ defm TRTT : SideEffectTernaryMemMemRRFcOpt<"trtt", 0xB990, GR128, GR64>;
+}
+
+let mayLoad = 1, mayStore = 1, Defs = [CC] in {
+ defm CU12 : SideEffectTernaryMemMemRRFcOpt<"cu12", 0xB2A7, GR128, GR128>;
+ defm CU14 : SideEffectTernaryMemMemRRFcOpt<"cu14", 0xB9B0, GR128, GR128>;
+ defm CU21 : SideEffectTernaryMemMemRRFcOpt<"cu21", 0xB2A6, GR128, GR128>;
+ defm CU24 : SideEffectTernaryMemMemRRFcOpt<"cu24", 0xB9B1, GR128, GR128>;
+ def CU41 : SideEffectBinaryMemMemRRE<"cu41", 0xB9B2, GR128, GR128>;
+ def CU42 : SideEffectBinaryMemMemRRE<"cu42", 0xB9B3, GR128, GR128>;
+
+ let isAsmParserOnly = 1 in {
+ defm CUUTF : SideEffectTernaryMemMemRRFcOpt<"cuutf", 0xB2A6, GR128, GR128>;
+ defm CUTFU : SideEffectTernaryMemMemRRFcOpt<"cutfu", 0xB2A7, GR128, GR128>;
+ }
+}
+
+//===----------------------------------------------------------------------===//
// Access registers
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ13.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ13.td?rev=302644&r1=302643&r2=302644&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ13.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ13.td Wed May 10 07:41:12 2017
@@ -565,6 +565,15 @@ def : InstRW<[FXb, FXb, LSU, Lat6, Group
def : InstRW<[LSU, LSU, Lat5, GroupAlone], (instregex "LPD(G)?$")>;
//===----------------------------------------------------------------------===//
+// Translate and convert
+//===----------------------------------------------------------------------===//
+
+def : InstRW<[FXa, Lat30, GroupAlone], (instregex "TR(T|TR)?(E|EOpt)?$")>;
+def : InstRW<[FXa, Lat30, GroupAlone], (instregex "TR(T|O)(T|O)(Opt)?$")>;
+def : InstRW<[FXa, Lat30, GroupAlone], (instregex "CU(12|14|21|24|41|42)(Opt)?$")>;
+def : InstRW<[FXa, Lat30, GroupAlone], (instregex "(CUUTF|CUTFU)(Opt)?$")>;
+
+//===----------------------------------------------------------------------===//
// Access registers
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ196.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ196.td?rev=302644&r1=302643&r2=302644&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ196.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ196.td Wed May 10 07:41:12 2017
@@ -522,6 +522,15 @@ def : InstRW<[FXU, FXU, LSU, LSU, Lat6,
def : InstRW<[LSU, LSU, Lat5, GroupAlone], (instregex "LPD(G)?$")>;
//===----------------------------------------------------------------------===//
+// Translate and convert
+//===----------------------------------------------------------------------===//
+
+def : InstRW<[FXU, Lat30, GroupAlone], (instregex "TR(T|TR)?(E|EOpt)?$")>;
+def : InstRW<[FXU, Lat30, GroupAlone], (instregex "TR(T|O)(T|O)(Opt)?$")>;
+def : InstRW<[FXU, Lat30, GroupAlone], (instregex "CU(12|14|21|24|41|42)(Opt)?$")>;
+def : InstRW<[FXU, Lat30, GroupAlone], (instregex "(CUUTF|CUTFU)(Opt)?$")>;
+
+//===----------------------------------------------------------------------===//
// Access registers
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/SystemZ/SystemZScheduleZEC12.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZScheduleZEC12.td?rev=302644&r1=302643&r2=302644&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZScheduleZEC12.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZScheduleZEC12.td Wed May 10 07:41:12 2017
@@ -534,6 +534,15 @@ def : InstRW<[FXU, FXU, LSU, LSU, Lat6,
def : InstRW<[LSU, LSU, Lat5, GroupAlone], (instregex "LPD(G)?$")>;
//===----------------------------------------------------------------------===//
+// Translate and convert
+//===----------------------------------------------------------------------===//
+
+def : InstRW<[FXU, Lat30, GroupAlone], (instregex "TR(T|TR)?(E|EOpt)?$")>;
+def : InstRW<[FXU, Lat30, GroupAlone], (instregex "TR(T|O)(T|O)(Opt)?$")>;
+def : InstRW<[FXU, Lat30, GroupAlone], (instregex "CU(12|14|21|24|41|42)(Opt)?$")>;
+def : InstRW<[FXU, Lat30, GroupAlone], (instregex "(CUUTF|CUTFU)(Opt)?$")>;
+
+//===----------------------------------------------------------------------===//
// Access registers
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt?rev=302644&r1=302643&r2=302644&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt (original)
+++ llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt Wed May 10 07:41:12 2017
@@ -3646,6 +3646,102 @@
# CHECK: csy %r15, %r0, 0
0xeb 0xf0 0x00 0x00 0x00 0x14
+# CHECK: cu12 %r0, %r0
+0xb2 0xa7 0x00 0x00
+
+# CHECK: cu12 %r0, %r14
+0xb2 0xa7 0x00 0x0e
+
+# CHECK: cu12 %r14, %r0
+0xb2 0xa7 0x00 0xe0
+
+# CHECK: cu12 %r6, %r8
+0xb2 0xa7 0x00 0x68
+
+# CHECK: cu12 %r4, %r12, 1
+0xb2 0xa7 0x10 0x4c
+
+# CHECK: cu12 %r4, %r12, 15
+0xb2 0xa7 0xf0 0x4c
+
+# CHECK: cu14 %r0, %r0
+0xb9 0xb0 0x00 0x00
+
+# CHECK: cu14 %r0, %r14
+0xb9 0xb0 0x00 0x0e
+
+# CHECK: cu14 %r14, %r0
+0xb9 0xb0 0x00 0xe0
+
+# CHECK: cu14 %r6, %r8
+0xb9 0xb0 0x00 0x68
+
+# CHECK: cu14 %r4, %r12, 1
+0xb9 0xb0 0x10 0x4c
+
+# CHECK: cu14 %r4, %r12, 15
+0xb9 0xb0 0xf0 0x4c
+
+# CHECK: cu21 %r0, %r0
+0xb2 0xa6 0x00 0x00
+
+# CHECK: cu21 %r0, %r14
+0xb2 0xa6 0x00 0x0e
+
+# CHECK: cu21 %r14, %r0
+0xb2 0xa6 0x00 0xe0
+
+# CHECK: cu21 %r6, %r8
+0xb2 0xa6 0x00 0x68
+
+# CHECK: cu21 %r4, %r12, 1
+0xb2 0xa6 0x10 0x4c
+
+# CHECK: cu21 %r4, %r12, 15
+0xb2 0xa6 0xf0 0x4c
+
+# CHECK: cu24 %r0, %r0
+0xb9 0xb1 0x00 0x00
+
+# CHECK: cu24 %r0, %r14
+0xb9 0xb1 0x00 0x0e
+
+# CHECK: cu24 %r14, %r0
+0xb9 0xb1 0x00 0xe0
+
+# CHECK: cu24 %r6, %r8
+0xb9 0xb1 0x00 0x68
+
+# CHECK: cu24 %r4, %r12, 1
+0xb9 0xb1 0x10 0x4c
+
+# CHECK: cu24 %r4, %r12, 15
+0xb9 0xb1 0xf0 0x4c
+
+# CHECK: cu41 %r0, %r0
+0xb9 0xb2 0x00 0x00
+
+# CHECK: cu41 %r0, %r14
+0xb9 0xb2 0x00 0x0e
+
+# CHECK: cu41 %r14, %r0
+0xb9 0xb2 0x00 0xe0
+
+# CHECK: cu41 %r6, %r8
+0xb9 0xb2 0x00 0x68
+
+# CHECK: cu42 %r0, %r0
+0xb9 0xb3 0x00 0x00
+
+# CHECK: cu42 %r0, %r14
+0xb9 0xb3 0x00 0x0e
+
+# CHECK: cu42 %r14, %r0
+0xb9 0xb3 0x00 0xe0
+
+# CHECK: cu42 %r6, %r8
+0xb9 0xb3 0x00 0x68
+
# CHECK: cuse %r0, %r0
0xb2 0x57 0x00 0x00
@@ -11305,6 +11401,234 @@
# CHECK: tmy 524287(%r15), 42
0xeb 0x2a 0xff 0xff 0x7f 0x51
+# CHECK: tr 0(1), 0
+0xdc 0x00 0x00 0x00 0x00 0x00
+
+# CHECK: tr 0(1), 0(%r1)
+0xdc 0x00 0x00 0x00 0x10 0x00
+
+# CHECK: tr 0(1), 0(%r15)
+0xdc 0x00 0x00 0x00 0xf0 0x00
+
+# CHECK: tr 0(1), 4095
+0xdc 0x00 0x00 0x00 0x0f 0xff
+
+# CHECK: tr 0(1), 4095(%r1)
+0xdc 0x00 0x00 0x00 0x1f 0xff
+
+# CHECK: tr 0(1), 4095(%r15)
+0xdc 0x00 0x00 0x00 0xff 0xff
+
+# CHECK: tr 0(1,%r1), 0
+0xdc 0x00 0x10 0x00 0x00 0x00
+
+# CHECK: tr 0(1,%r15), 0
+0xdc 0x00 0xf0 0x00 0x00 0x00
+
+# CHECK: tr 4095(1,%r1), 0
+0xdc 0x00 0x1f 0xff 0x00 0x00
+
+# CHECK: tr 4095(1,%r15), 0
+0xdc 0x00 0xff 0xff 0x00 0x00
+
+# CHECK: tr 0(256,%r1), 0
+0xdc 0xff 0x10 0x00 0x00 0x00
+
+# CHECK: tr 0(256,%r15), 0
+0xdc 0xff 0xf0 0x00 0x00 0x00
+
+# CHECK: tre %r0, %r0
+0xb2 0xa5 0x00 0x00
+
+# CHECK: tre %r0, %r15
+0xb2 0xa5 0x00 0x0f
+
+# CHECK: tre %r14, %r0
+0xb2 0xa5 0x00 0xe0
+
+# CHECK: tre %r6, %r8
+0xb2 0xa5 0x00 0x68
+
+# CHECK: troo %r0, %r0
+0xb9 0x93 0x00 0x00
+
+# CHECK: troo %r0, %r15
+0xb9 0x93 0x00 0x0f
+
+# CHECK: troo %r14, %r0
+0xb9 0x93 0x00 0xe0
+
+# CHECK: troo %r6, %r8
+0xb9 0x93 0x00 0x68
+
+# CHECK: troo %r4, %r12, 1
+0xb9 0x93 0x10 0x4c
+
+# CHECK: troo %r4, %r12, 15
+0xb9 0x93 0xf0 0x4c
+
+# CHECK: trot %r0, %r0
+0xb9 0x92 0x00 0x00
+
+# CHECK: trot %r0, %r15
+0xb9 0x92 0x00 0x0f
+
+# CHECK: trot %r14, %r0
+0xb9 0x92 0x00 0xe0
+
+# CHECK: trot %r6, %r8
+0xb9 0x92 0x00 0x68
+
+# CHECK: trot %r4, %r12, 1
+0xb9 0x92 0x10 0x4c
+
+# CHECK: trot %r4, %r12, 15
+0xb9 0x92 0xf0 0x4c
+
+# CHECK: trt 0(1), 0
+0xdd 0x00 0x00 0x00 0x00 0x00
+
+# CHECK: trt 0(1), 0(%r1)
+0xdd 0x00 0x00 0x00 0x10 0x00
+
+# CHECK: trt 0(1), 0(%r15)
+0xdd 0x00 0x00 0x00 0xf0 0x00
+
+# CHECK: trt 0(1), 4095
+0xdd 0x00 0x00 0x00 0x0f 0xff
+
+# CHECK: trt 0(1), 4095(%r1)
+0xdd 0x00 0x00 0x00 0x1f 0xff
+
+# CHECK: trt 0(1), 4095(%r15)
+0xdd 0x00 0x00 0x00 0xff 0xff
+
+# CHECK: trt 0(1,%r1), 0
+0xdd 0x00 0x10 0x00 0x00 0x00
+
+# CHECK: trt 0(1,%r15), 0
+0xdd 0x00 0xf0 0x00 0x00 0x00
+
+# CHECK: trt 4095(1,%r1), 0
+0xdd 0x00 0x1f 0xff 0x00 0x00
+
+# CHECK: trt 4095(1,%r15), 0
+0xdd 0x00 0xff 0xff 0x00 0x00
+
+# CHECK: trt 0(256,%r1), 0
+0xdd 0xff 0x10 0x00 0x00 0x00
+
+# CHECK: trt 0(256,%r15), 0
+0xdd 0xff 0xf0 0x00 0x00 0x00
+
+# CHECK: trte %r0, %r0
+0xb9 0xbf 0x00 0x00
+
+# CHECK: trte %r0, %r15
+0xb9 0xbf 0x00 0x0f
+
+# CHECK: trte %r14, %r0
+0xb9 0xbf 0x00 0xe0
+
+# CHECK: trte %r6, %r8
+0xb9 0xbf 0x00 0x68
+
+# CHECK: trte %r4, %r12, 1
+0xb9 0xbf 0x10 0x4c
+
+# CHECK: trte %r4, %r12, 15
+0xb9 0xbf 0xf0 0x4c
+
+# CHECK: trto %r0, %r0
+0xb9 0x91 0x00 0x00
+
+# CHECK: trto %r0, %r15
+0xb9 0x91 0x00 0x0f
+
+# CHECK: trto %r14, %r0
+0xb9 0x91 0x00 0xe0
+
+# CHECK: trto %r6, %r8
+0xb9 0x91 0x00 0x68
+
+# CHECK: trto %r4, %r12, 1
+0xb9 0x91 0x10 0x4c
+
+# CHECK: trto %r4, %r12, 15
+0xb9 0x91 0xf0 0x4c
+
+# CHECK: trtr 0(1), 0
+0xd0 0x00 0x00 0x00 0x00 0x00
+
+# CHECK: trtr 0(1), 0(%r1)
+0xd0 0x00 0x00 0x00 0x10 0x00
+
+# CHECK: trtr 0(1), 0(%r15)
+0xd0 0x00 0x00 0x00 0xf0 0x00
+
+# CHECK: trtr 0(1), 4095
+0xd0 0x00 0x00 0x00 0x0f 0xff
+
+# CHECK: trtr 0(1), 4095(%r1)
+0xd0 0x00 0x00 0x00 0x1f 0xff
+
+# CHECK: trtr 0(1), 4095(%r15)
+0xd0 0x00 0x00 0x00 0xff 0xff
+
+# CHECK: trtr 0(1,%r1), 0
+0xd0 0x00 0x10 0x00 0x00 0x00
+
+# CHECK: trtr 0(1,%r15), 0
+0xd0 0x00 0xf0 0x00 0x00 0x00
+
+# CHECK: trtr 4095(1,%r1), 0
+0xd0 0x00 0x1f 0xff 0x00 0x00
+
+# CHECK: trtr 4095(1,%r15), 0
+0xd0 0x00 0xff 0xff 0x00 0x00
+
+# CHECK: trtr 0(256,%r1), 0
+0xd0 0xff 0x10 0x00 0x00 0x00
+
+# CHECK: trtr 0(256,%r15), 0
+0xd0 0xff 0xf0 0x00 0x00 0x00
+
+# CHECK: trtre %r0, %r0
+0xb9 0xbd 0x00 0x00
+
+# CHECK: trtre %r0, %r15
+0xb9 0xbd 0x00 0x0f
+
+# CHECK: trtre %r14, %r0
+0xb9 0xbd 0x00 0xe0
+
+# CHECK: trtre %r6, %r8
+0xb9 0xbd 0x00 0x68
+
+# CHECK: trtre %r4, %r12, 1
+0xb9 0xbd 0x10 0x4c
+
+# CHECK: trtre %r4, %r12, 15
+0xb9 0xbd 0xf0 0x4c
+
+# CHECK: trtt %r0, %r0
+0xb9 0x90 0x00 0x00
+
+# CHECK: trtt %r0, %r15
+0xb9 0x90 0x00 0x0f
+
+# CHECK: trtt %r14, %r0
+0xb9 0x90 0x00 0xe0
+
+# CHECK: trtt %r6, %r8
+0xb9 0x90 0x00 0x68
+
+# CHECK: trtt %r4, %r12, 1
+0xb9 0x90 0x10 0x4c
+
+# CHECK: trtt %r4, %r12, 15
+0xb9 0x90 0xf0 0x4c
+
# CHECK: ts 0
0x93 0x00 0x00 0x00
Modified: llvm/trunk/test/MC/SystemZ/insn-bad.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/SystemZ/insn-bad.s?rev=302644&r1=302643&r2=302644&view=diff
==============================================================================
--- llvm/trunk/test/MC/SystemZ/insn-bad.s (original)
+++ llvm/trunk/test/MC/SystemZ/insn-bad.s Wed May 10 07:41:12 2017
@@ -1587,6 +1587,78 @@
csy %r0, %r0, 0(%r1,%r2)
#CHECK: error: invalid register pair
+#CHECK: cu12 %r1, %r0
+#CHECK: error: invalid register pair
+#CHECK: cu12 %r0, %r1
+#CHECK: error: invalid operand
+#CHECK: cu12 %r2, %r4, -1
+#CHECK: error: invalid operand
+#CHECK: cu12 %r2, %r4, 16
+
+ cu12 %r1, %r0
+ cu12 %r0, %r1
+ cu12 %r2, %r4, -1
+ cu12 %r2, %r4, 16
+
+#CHECK: error: invalid register pair
+#CHECK: cu14 %r1, %r0
+#CHECK: error: invalid register pair
+#CHECK: cu14 %r0, %r1
+#CHECK: error: invalid operand
+#CHECK: cu14 %r2, %r4, -1
+#CHECK: error: invalid operand
+#CHECK: cu14 %r2, %r4, 16
+
+ cu14 %r1, %r0
+ cu14 %r0, %r1
+ cu14 %r2, %r4, -1
+ cu14 %r2, %r4, 16
+
+#CHECK: error: invalid register pair
+#CHECK: cu21 %r1, %r0
+#CHECK: error: invalid register pair
+#CHECK: cu21 %r0, %r1
+#CHECK: error: invalid operand
+#CHECK: cu21 %r2, %r4, -1
+#CHECK: error: invalid operand
+#CHECK: cu21 %r2, %r4, 16
+
+ cu21 %r1, %r0
+ cu21 %r0, %r1
+ cu21 %r2, %r4, -1
+ cu21 %r2, %r4, 16
+
+#CHECK: error: invalid register pair
+#CHECK: cu24 %r1, %r0
+#CHECK: error: invalid register pair
+#CHECK: cu24 %r0, %r1
+#CHECK: error: invalid operand
+#CHECK: cu24 %r2, %r4, -1
+#CHECK: error: invalid operand
+#CHECK: cu24 %r2, %r4, 16
+
+ cu24 %r1, %r0
+ cu24 %r0, %r1
+ cu24 %r2, %r4, -1
+ cu24 %r2, %r4, 16
+
+#CHECK: error: invalid register pair
+#CHECK: cu41 %r1, %r0
+#CHECK: error: invalid register pair
+#CHECK: cu41 %r0, %r1
+
+ cu41 %r1, %r0
+ cu41 %r0, %r1
+
+#CHECK: error: invalid register pair
+#CHECK: cu42 %r1, %r0
+#CHECK: error: invalid register pair
+#CHECK: cu42 %r0, %r1
+
+ cu42 %r1, %r0
+ cu42 %r0, %r1
+
+#CHECK: error: invalid register pair
#CHECK: cuse %r1, %r0
#CHECK: error: invalid register pair
#CHECK: cuse %r0, %r1
@@ -1595,6 +1667,34 @@
cuse %r0, %r1
#CHECK: error: invalid register pair
+#CHECK: cutfu %r1, %r0
+#CHECK: error: invalid register pair
+#CHECK: cutfu %r0, %r1
+#CHECK: error: invalid operand
+#CHECK: cutfu %r2, %r4, -1
+#CHECK: error: invalid operand
+#CHECK: cutfu %r2, %r4, 16
+
+ cutfu %r1, %r0
+ cutfu %r0, %r1
+ cutfu %r2, %r4, -1
+ cutfu %r2, %r4, 16
+
+#CHECK: error: invalid register pair
+#CHECK: cuutf %r1, %r0
+#CHECK: error: invalid register pair
+#CHECK: cuutf %r0, %r1
+#CHECK: error: invalid operand
+#CHECK: cuutf %r2, %r4, -1
+#CHECK: error: invalid operand
+#CHECK: cuutf %r2, %r4, 16
+
+ cuutf %r1, %r0
+ cuutf %r0, %r1
+ cuutf %r2, %r4, -1
+ cuutf %r2, %r4, 16
+
+#CHECK: error: invalid register pair
#CHECK: cxbr %f0, %f2
#CHECK: error: invalid register pair
#CHECK: cxbr %f2, %f0
@@ -4196,6 +4296,209 @@
tmy 0, -1
tmy 0, 256
+#CHECK: error: missing length in address
+#CHECK: tr 0, 0
+#CHECK: error: missing length in address
+#CHECK: tr 0(%r1), 0(%r1)
+#CHECK: error: invalid use of length addressing
+#CHECK: tr 0(1,%r1), 0(2,%r1)
+#CHECK: error: invalid operand
+#CHECK: tr 0(0,%r1), 0(%r1)
+#CHECK: error: invalid operand
+#CHECK: tr 0(257,%r1), 0(%r1)
+#CHECK: error: invalid operand
+#CHECK: tr -1(1,%r1), 0(%r1)
+#CHECK: error: invalid operand
+#CHECK: tr 4096(1,%r1), 0(%r1)
+#CHECK: error: invalid operand
+#CHECK: tr 0(1,%r1), -1(%r1)
+#CHECK: error: invalid operand
+#CHECK: tr 0(1,%r1), 4096(%r1)
+#CHECK: error: %r0 used in an address
+#CHECK: tr 0(1,%r0), 0(%r1)
+#CHECK: error: %r0 used in an address
+#CHECK: tr 0(1,%r1), 0(%r0)
+#CHECK: error: invalid use of indexed addressing
+#CHECK: tr 0(%r1,%r2), 0(%r1)
+#CHECK: error: invalid use of indexed addressing
+#CHECK: tr 0(1,%r2), 0(%r1,%r2)
+#CHECK: error: unknown token in expression
+#CHECK: tr 0(-), 0
+
+ tr 0, 0
+ tr 0(%r1), 0(%r1)
+ tr 0(1,%r1), 0(2,%r1)
+ tr 0(0,%r1), 0(%r1)
+ tr 0(257,%r1), 0(%r1)
+ tr -1(1,%r1), 0(%r1)
+ tr 4096(1,%r1), 0(%r1)
+ tr 0(1,%r1), -1(%r1)
+ tr 0(1,%r1), 4096(%r1)
+ tr 0(1,%r0), 0(%r1)
+ tr 0(1,%r1), 0(%r0)
+ tr 0(%r1,%r2), 0(%r1)
+ tr 0(1,%r2), 0(%r1,%r2)
+ tr 0(-), 0
+
+#CHECK: error: invalid register pair
+#CHECK: tre %r1, %r0
+
+ tre %r1, %r0
+
+#CHECK: error: invalid register pair
+#CHECK: troo %r1, %r0
+#CHECK: error: invalid operand
+#CHECK: troo %r2, %r4, -1
+#CHECK: error: invalid operand
+#CHECK: troo %r2, %r4, 16
+
+ troo %r1, %r0
+ troo %r2, %r4, -1
+ troo %r2, %r4, 16
+
+#CHECK: error: invalid register pair
+#CHECK: trot %r1, %r0
+#CHECK: error: invalid operand
+#CHECK: trot %r2, %r4, -1
+#CHECK: error: invalid operand
+#CHECK: trot %r2, %r4, 16
+
+ trot %r1, %r0
+ trot %r2, %r4, -1
+ trot %r2, %r4, 16
+
+#CHECK: error: missing length in address
+#CHECK: trt 0, 0
+#CHECK: error: missing length in address
+#CHECK: trt 0(%r1), 0(%r1)
+#CHECK: error: invalid use of length addressing
+#CHECK: trt 0(1,%r1), 0(2,%r1)
+#CHECK: error: invalid operand
+#CHECK: trt 0(0,%r1), 0(%r1)
+#CHECK: error: invalid operand
+#CHECK: trt 0(257,%r1), 0(%r1)
+#CHECK: error: invalid operand
+#CHECK: trt -1(1,%r1), 0(%r1)
+#CHECK: error: invalid operand
+#CHECK: trt 4096(1,%r1), 0(%r1)
+#CHECK: error: invalid operand
+#CHECK: trt 0(1,%r1), -1(%r1)
+#CHECK: error: invalid operand
+#CHECK: trt 0(1,%r1), 4096(%r1)
+#CHECK: error: %r0 used in an address
+#CHECK: trt 0(1,%r0), 0(%r1)
+#CHECK: error: %r0 used in an address
+#CHECK: trt 0(1,%r1), 0(%r0)
+#CHECK: error: invalid use of indexed addressing
+#CHECK: trt 0(%r1,%r2), 0(%r1)
+#CHECK: error: invalid use of indexed addressing
+#CHECK: trt 0(1,%r2), 0(%r1,%r2)
+#CHECK: error: unknown token in expression
+#CHECK: trt 0(-), 0
+
+ trt 0, 0
+ trt 0(%r1), 0(%r1)
+ trt 0(1,%r1), 0(2,%r1)
+ trt 0(0,%r1), 0(%r1)
+ trt 0(257,%r1), 0(%r1)
+ trt -1(1,%r1), 0(%r1)
+ trt 4096(1,%r1), 0(%r1)
+ trt 0(1,%r1), -1(%r1)
+ trt 0(1,%r1), 4096(%r1)
+ trt 0(1,%r0), 0(%r1)
+ trt 0(1,%r1), 0(%r0)
+ trt 0(%r1,%r2), 0(%r1)
+ trt 0(1,%r2), 0(%r1,%r2)
+ trt 0(-), 0
+
+#CHECK: error: invalid register pair
+#CHECK: trte %r1, %r0
+#CHECK: error: invalid operand
+#CHECK: trte %r2, %r4, -1
+#CHECK: error: invalid operand
+#CHECK: trte %r2, %r4, 16
+
+ trte %r1, %r0
+ trte %r2, %r4, -1
+ trte %r2, %r4, 16
+
+#CHECK: error: invalid register pair
+#CHECK: trto %r1, %r0
+#CHECK: error: invalid operand
+#CHECK: trto %r2, %r4, -1
+#CHECK: error: invalid operand
+#CHECK: trto %r2, %r4, 16
+
+ trto %r1, %r0
+ trto %r2, %r4, -1
+ trto %r2, %r4, 16
+
+#CHECK: error: missing length in address
+#CHECK: trtr 0, 0
+#CHECK: error: missing length in address
+#CHECK: trtr 0(%r1), 0(%r1)
+#CHECK: error: invalid use of length addressing
+#CHECK: trtr 0(1,%r1), 0(2,%r1)
+#CHECK: error: invalid operand
+#CHECK: trtr 0(0,%r1), 0(%r1)
+#CHECK: error: invalid operand
+#CHECK: trtr 0(257,%r1), 0(%r1)
+#CHECK: error: invalid operand
+#CHECK: trtr -1(1,%r1), 0(%r1)
+#CHECK: error: invalid operand
+#CHECK: trtr 4096(1,%r1), 0(%r1)
+#CHECK: error: invalid operand
+#CHECK: trtr 0(1,%r1), -1(%r1)
+#CHECK: error: invalid operand
+#CHECK: trtr 0(1,%r1), 4096(%r1)
+#CHECK: error: %r0 used in an address
+#CHECK: trtr 0(1,%r0), 0(%r1)
+#CHECK: error: %r0 used in an address
+#CHECK: trtr 0(1,%r1), 0(%r0)
+#CHECK: error: invalid use of indexed addressing
+#CHECK: trtr 0(%r1,%r2), 0(%r1)
+#CHECK: error: invalid use of indexed addressing
+#CHECK: trtr 0(1,%r2), 0(%r1,%r2)
+#CHECK: error: unknown token in expression
+#CHECK: trtr 0(-), 0
+
+ trtr 0, 0
+ trtr 0(%r1), 0(%r1)
+ trtr 0(1,%r1), 0(2,%r1)
+ trtr 0(0,%r1), 0(%r1)
+ trtr 0(257,%r1), 0(%r1)
+ trtr -1(1,%r1), 0(%r1)
+ trtr 4096(1,%r1), 0(%r1)
+ trtr 0(1,%r1), -1(%r1)
+ trtr 0(1,%r1), 4096(%r1)
+ trtr 0(1,%r0), 0(%r1)
+ trtr 0(1,%r1), 0(%r0)
+ trtr 0(%r1,%r2), 0(%r1)
+ trtr 0(1,%r2), 0(%r1,%r2)
+ trtr 0(-), 0
+
+#CHECK: error: invalid register pair
+#CHECK: trtre %r1, %r0
+#CHECK: error: invalid operand
+#CHECK: trtre %r2, %r4, -1
+#CHECK: error: invalid operand
+#CHECK: trtre %r2, %r4, 16
+
+ trtre %r1, %r0
+ trtre %r2, %r4, -1
+ trtre %r2, %r4, 16
+
+#CHECK: error: invalid register pair
+#CHECK: trtt %r1, %r0
+#CHECK: error: invalid operand
+#CHECK: trtt %r2, %r4, -1
+#CHECK: error: invalid operand
+#CHECK: trtt %r2, %r4, 16
+
+ trtt %r1, %r0
+ trtt %r2, %r4, -1
+ trtt %r2, %r4, 16
+
#CHECK: error: invalid operand
#CHECK: ts -1
#CHECK: error: invalid operand
Modified: llvm/trunk/test/MC/SystemZ/insn-good.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/SystemZ/insn-good.s?rev=302644&r1=302643&r2=302644&view=diff
==============================================================================
--- llvm/trunk/test/MC/SystemZ/insn-good.s (original)
+++ llvm/trunk/test/MC/SystemZ/insn-good.s Wed May 10 07:41:12 2017
@@ -5709,6 +5709,82 @@
csy %r0, %r15, 0
csy %r15, %r0, 0
+#CHECK: cu12 %r0, %r0 # encoding: [0xb2,0xa7,0x00,0x00]
+#CHECK: cu12 %r0, %r14 # encoding: [0xb2,0xa7,0x00,0x0e]
+#CHECK: cu12 %r14, %r0 # encoding: [0xb2,0xa7,0x00,0xe0]
+#CHECK: cu12 %r6, %r8 # encoding: [0xb2,0xa7,0x00,0x68]
+#CHECK: cu12 %r4, %r12, 0 # encoding: [0xb2,0xa7,0x00,0x4c]
+#CHECK: cu12 %r4, %r12, 15 # encoding: [0xb2,0xa7,0xf0,0x4c]
+
+ cu12 %r0, %r0
+ cu12 %r0, %r14
+ cu12 %r14, %r0
+ cu12 %r6, %r8
+ cu12 %r4, %r12, 0
+ cu12 %r4, %r12, 15
+
+#CHECK: cu14 %r0, %r0 # encoding: [0xb9,0xb0,0x00,0x00]
+#CHECK: cu14 %r0, %r14 # encoding: [0xb9,0xb0,0x00,0x0e]
+#CHECK: cu14 %r14, %r0 # encoding: [0xb9,0xb0,0x00,0xe0]
+#CHECK: cu14 %r6, %r8 # encoding: [0xb9,0xb0,0x00,0x68]
+#CHECK: cu14 %r4, %r12, 0 # encoding: [0xb9,0xb0,0x00,0x4c]
+#CHECK: cu14 %r4, %r12, 15 # encoding: [0xb9,0xb0,0xf0,0x4c]
+
+ cu14 %r0, %r0
+ cu14 %r0, %r14
+ cu14 %r14, %r0
+ cu14 %r6, %r8
+ cu14 %r4, %r12, 0
+ cu14 %r4, %r12, 15
+
+#CHECK: cu21 %r0, %r0 # encoding: [0xb2,0xa6,0x00,0x00]
+#CHECK: cu21 %r0, %r14 # encoding: [0xb2,0xa6,0x00,0x0e]
+#CHECK: cu21 %r14, %r0 # encoding: [0xb2,0xa6,0x00,0xe0]
+#CHECK: cu21 %r6, %r8 # encoding: [0xb2,0xa6,0x00,0x68]
+#CHECK: cu21 %r4, %r12, 0 # encoding: [0xb2,0xa6,0x00,0x4c]
+#CHECK: cu21 %r4, %r12, 15 # encoding: [0xb2,0xa6,0xf0,0x4c]
+
+ cu21 %r0, %r0
+ cu21 %r0, %r14
+ cu21 %r14, %r0
+ cu21 %r6, %r8
+ cu21 %r4, %r12, 0
+ cu21 %r4, %r12, 15
+
+#CHECK: cu24 %r0, %r0 # encoding: [0xb9,0xb1,0x00,0x00]
+#CHECK: cu24 %r0, %r14 # encoding: [0xb9,0xb1,0x00,0x0e]
+#CHECK: cu24 %r14, %r0 # encoding: [0xb9,0xb1,0x00,0xe0]
+#CHECK: cu24 %r6, %r8 # encoding: [0xb9,0xb1,0x00,0x68]
+#CHECK: cu24 %r4, %r12, 0 # encoding: [0xb9,0xb1,0x00,0x4c]
+#CHECK: cu24 %r4, %r12, 15 # encoding: [0xb9,0xb1,0xf0,0x4c]
+
+ cu24 %r0, %r0
+ cu24 %r0, %r14
+ cu24 %r14, %r0
+ cu24 %r6, %r8
+ cu24 %r4, %r12, 0
+ cu24 %r4, %r12, 15
+
+#CHECK: cu41 %r0, %r0 # encoding: [0xb9,0xb2,0x00,0x00]
+#CHECK: cu41 %r0, %r14 # encoding: [0xb9,0xb2,0x00,0x0e]
+#CHECK: cu41 %r14, %r0 # encoding: [0xb9,0xb2,0x00,0xe0]
+#CHECK: cu41 %r6, %r8 # encoding: [0xb9,0xb2,0x00,0x68]
+
+ cu41 %r0, %r0
+ cu41 %r0, %r14
+ cu41 %r14, %r0
+ cu41 %r6, %r8
+
+#CHECK: cu42 %r0, %r0 # encoding: [0xb9,0xb3,0x00,0x00]
+#CHECK: cu42 %r0, %r14 # encoding: [0xb9,0xb3,0x00,0x0e]
+#CHECK: cu42 %r14, %r0 # encoding: [0xb9,0xb3,0x00,0xe0]
+#CHECK: cu42 %r6, %r8 # encoding: [0xb9,0xb3,0x00,0x68]
+
+ cu42 %r0, %r0
+ cu42 %r0, %r14
+ cu42 %r14, %r0
+ cu42 %r6, %r8
+
#CHECK: cuse %r0, %r8 # encoding: [0xb2,0x57,0x00,0x08]
#CHECK: cuse %r0, %r14 # encoding: [0xb2,0x57,0x00,0x0e]
#CHECK: cuse %r14, %r0 # encoding: [0xb2,0x57,0x00,0xe0]
@@ -5719,6 +5795,34 @@
cuse %r14, %r0
cuse %r14, %r8
+#CHECK: cutfu %r0, %r0 # encoding: [0xb2,0xa7,0x00,0x00]
+#CHECK: cutfu %r0, %r14 # encoding: [0xb2,0xa7,0x00,0x0e]
+#CHECK: cutfu %r14, %r0 # encoding: [0xb2,0xa7,0x00,0xe0]
+#CHECK: cutfu %r6, %r8 # encoding: [0xb2,0xa7,0x00,0x68]
+#CHECK: cutfu %r4, %r12, 0 # encoding: [0xb2,0xa7,0x00,0x4c]
+#CHECK: cutfu %r4, %r12, 15 # encoding: [0xb2,0xa7,0xf0,0x4c]
+
+ cutfu %r0, %r0
+ cutfu %r0, %r14
+ cutfu %r14, %r0
+ cutfu %r6, %r8
+ cutfu %r4, %r12, 0
+ cutfu %r4, %r12, 15
+
+#CHECK: cuutf %r0, %r0 # encoding: [0xb2,0xa6,0x00,0x00]
+#CHECK: cuutf %r0, %r14 # encoding: [0xb2,0xa6,0x00,0x0e]
+#CHECK: cuutf %r14, %r0 # encoding: [0xb2,0xa6,0x00,0xe0]
+#CHECK: cuutf %r6, %r8 # encoding: [0xb2,0xa6,0x00,0x68]
+#CHECK: cuutf %r4, %r12, 0 # encoding: [0xb2,0xa6,0x00,0x4c]
+#CHECK: cuutf %r4, %r12, 15 # encoding: [0xb2,0xa6,0xf0,0x4c]
+
+ cuutf %r0, %r0
+ cuutf %r0, %r14
+ cuutf %r14, %r0
+ cuutf %r6, %r8
+ cuutf %r4, %r12, 0
+ cuutf %r4, %r12, 15
+
#CHECK: cxbr %f0, %f0 # encoding: [0xb3,0x49,0x00,0x00]
#CHECK: cxbr %f0, %f13 # encoding: [0xb3,0x49,0x00,0x0d]
#CHECK: cxbr %f8, %f8 # encoding: [0xb3,0x49,0x00,0x88]
@@ -10875,6 +10979,178 @@
tmy 524287(%r1), 42
tmy 524287(%r15), 42
+#CHECK: tr 0(1), 0 # encoding: [0xdc,0x00,0x00,0x00,0x00,0x00]
+#CHECK: tr 0(1), 0(%r1) # encoding: [0xdc,0x00,0x00,0x00,0x10,0x00]
+#CHECK: tr 0(1), 0(%r15) # encoding: [0xdc,0x00,0x00,0x00,0xf0,0x00]
+#CHECK: tr 0(1), 4095 # encoding: [0xdc,0x00,0x00,0x00,0x0f,0xff]
+#CHECK: tr 0(1), 4095(%r1) # encoding: [0xdc,0x00,0x00,0x00,0x1f,0xff]
+#CHECK: tr 0(1), 4095(%r15) # encoding: [0xdc,0x00,0x00,0x00,0xff,0xff]
+#CHECK: tr 0(1,%r1), 0 # encoding: [0xdc,0x00,0x10,0x00,0x00,0x00]
+#CHECK: tr 0(1,%r15), 0 # encoding: [0xdc,0x00,0xf0,0x00,0x00,0x00]
+#CHECK: tr 4095(1,%r1), 0 # encoding: [0xdc,0x00,0x1f,0xff,0x00,0x00]
+#CHECK: tr 4095(1,%r15), 0 # encoding: [0xdc,0x00,0xff,0xff,0x00,0x00]
+#CHECK: tr 0(256,%r1), 0 # encoding: [0xdc,0xff,0x10,0x00,0x00,0x00]
+#CHECK: tr 0(256,%r15), 0 # encoding: [0xdc,0xff,0xf0,0x00,0x00,0x00]
+
+ tr 0(1), 0
+ tr 0(1), 0(%r1)
+ tr 0(1), 0(%r15)
+ tr 0(1), 4095
+ tr 0(1), 4095(%r1)
+ tr 0(1), 4095(%r15)
+ tr 0(1,%r1), 0
+ tr 0(1,%r15), 0
+ tr 4095(1,%r1), 0
+ tr 4095(1,%r15), 0
+ tr 0(256,%r1), 0
+ tr 0(256,%r15), 0
+
+#CHECK: tre %r0, %r0 # encoding: [0xb2,0xa5,0x00,0x00]
+#CHECK: tre %r0, %r15 # encoding: [0xb2,0xa5,0x00,0x0f]
+#CHECK: tre %r14, %r0 # encoding: [0xb2,0xa5,0x00,0xe0]
+#CHECK: tre %r6, %r8 # encoding: [0xb2,0xa5,0x00,0x68]
+
+ tre %r0, %r0
+ tre %r0, %r15
+ tre %r14, %r0
+ tre %r6, %r8
+
+#CHECK: troo %r0, %r0 # encoding: [0xb9,0x93,0x00,0x00]
+#CHECK: troo %r0, %r15 # encoding: [0xb9,0x93,0x00,0x0f]
+#CHECK: troo %r14, %r0 # encoding: [0xb9,0x93,0x00,0xe0]
+#CHECK: troo %r6, %r8 # encoding: [0xb9,0x93,0x00,0x68]
+#CHECK: troo %r4, %r13, 0 # encoding: [0xb9,0x93,0x00,0x4d]
+#CHECK: troo %r4, %r13, 15 # encoding: [0xb9,0x93,0xf0,0x4d]
+
+ troo %r0, %r0
+ troo %r0, %r15
+ troo %r14, %r0
+ troo %r6, %r8
+ troo %r4, %r13, 0
+ troo %r4, %r13, 15
+
+#CHECK: trot %r0, %r0 # encoding: [0xb9,0x92,0x00,0x00]
+#CHECK: trot %r0, %r15 # encoding: [0xb9,0x92,0x00,0x0f]
+#CHECK: trot %r14, %r0 # encoding: [0xb9,0x92,0x00,0xe0]
+#CHECK: trot %r6, %r8 # encoding: [0xb9,0x92,0x00,0x68]
+#CHECK: trot %r4, %r13, 0 # encoding: [0xb9,0x92,0x00,0x4d]
+#CHECK: trot %r4, %r13, 15 # encoding: [0xb9,0x92,0xf0,0x4d]
+
+ trot %r0, %r0
+ trot %r0, %r15
+ trot %r14, %r0
+ trot %r6, %r8
+ trot %r4, %r13, 0
+ trot %r4, %r13, 15
+
+#CHECK: trt 0(1), 0 # encoding: [0xdd,0x00,0x00,0x00,0x00,0x00]
+#CHECK: trt 0(1), 0(%r1) # encoding: [0xdd,0x00,0x00,0x00,0x10,0x00]
+#CHECK: trt 0(1), 0(%r15) # encoding: [0xdd,0x00,0x00,0x00,0xf0,0x00]
+#CHECK: trt 0(1), 4095 # encoding: [0xdd,0x00,0x00,0x00,0x0f,0xff]
+#CHECK: trt 0(1), 4095(%r1) # encoding: [0xdd,0x00,0x00,0x00,0x1f,0xff]
+#CHECK: trt 0(1), 4095(%r15) # encoding: [0xdd,0x00,0x00,0x00,0xff,0xff]
+#CHECK: trt 0(1,%r1), 0 # encoding: [0xdd,0x00,0x10,0x00,0x00,0x00]
+#CHECK: trt 0(1,%r15), 0 # encoding: [0xdd,0x00,0xf0,0x00,0x00,0x00]
+#CHECK: trt 4095(1,%r1), 0 # encoding: [0xdd,0x00,0x1f,0xff,0x00,0x00]
+#CHECK: trt 4095(1,%r15), 0 # encoding: [0xdd,0x00,0xff,0xff,0x00,0x00]
+#CHECK: trt 0(256,%r1), 0 # encoding: [0xdd,0xff,0x10,0x00,0x00,0x00]
+#CHECK: trt 0(256,%r15), 0 # encoding: [0xdd,0xff,0xf0,0x00,0x00,0x00]
+
+ trt 0(1), 0
+ trt 0(1), 0(%r1)
+ trt 0(1), 0(%r15)
+ trt 0(1), 4095
+ trt 0(1), 4095(%r1)
+ trt 0(1), 4095(%r15)
+ trt 0(1,%r1), 0
+ trt 0(1,%r15), 0
+ trt 4095(1,%r1), 0
+ trt 4095(1,%r15), 0
+ trt 0(256,%r1), 0
+ trt 0(256,%r15), 0
+
+#CHECK: trte %r0, %r0 # encoding: [0xb9,0xbf,0x00,0x00]
+#CHECK: trte %r0, %r15 # encoding: [0xb9,0xbf,0x00,0x0f]
+#CHECK: trte %r14, %r0 # encoding: [0xb9,0xbf,0x00,0xe0]
+#CHECK: trte %r6, %r8 # encoding: [0xb9,0xbf,0x00,0x68]
+#CHECK: trte %r4, %r13, 0 # encoding: [0xb9,0xbf,0x00,0x4d]
+#CHECK: trte %r4, %r13, 15 # encoding: [0xb9,0xbf,0xf0,0x4d]
+
+ trte %r0, %r0
+ trte %r0, %r15
+ trte %r14, %r0
+ trte %r6, %r8
+ trte %r4, %r13, 0
+ trte %r4, %r13, 15
+
+#CHECK: trto %r0, %r0 # encoding: [0xb9,0x91,0x00,0x00]
+#CHECK: trto %r0, %r15 # encoding: [0xb9,0x91,0x00,0x0f]
+#CHECK: trto %r14, %r0 # encoding: [0xb9,0x91,0x00,0xe0]
+#CHECK: trto %r6, %r8 # encoding: [0xb9,0x91,0x00,0x68]
+#CHECK: trto %r4, %r13, 0 # encoding: [0xb9,0x91,0x00,0x4d]
+#CHECK: trto %r4, %r13, 15 # encoding: [0xb9,0x91,0xf0,0x4d]
+
+ trto %r0, %r0
+ trto %r0, %r15
+ trto %r14, %r0
+ trto %r6, %r8
+ trto %r4, %r13, 0
+ trto %r4, %r13, 15
+
+#CHECK: trtr 0(1), 0 # encoding: [0xd0,0x00,0x00,0x00,0x00,0x00]
+#CHECK: trtr 0(1), 0(%r1) # encoding: [0xd0,0x00,0x00,0x00,0x10,0x00]
+#CHECK: trtr 0(1), 0(%r15) # encoding: [0xd0,0x00,0x00,0x00,0xf0,0x00]
+#CHECK: trtr 0(1), 4095 # encoding: [0xd0,0x00,0x00,0x00,0x0f,0xff]
+#CHECK: trtr 0(1), 4095(%r1) # encoding: [0xd0,0x00,0x00,0x00,0x1f,0xff]
+#CHECK: trtr 0(1), 4095(%r15) # encoding: [0xd0,0x00,0x00,0x00,0xff,0xff]
+#CHECK: trtr 0(1,%r1), 0 # encoding: [0xd0,0x00,0x10,0x00,0x00,0x00]
+#CHECK: trtr 0(1,%r15), 0 # encoding: [0xd0,0x00,0xf0,0x00,0x00,0x00]
+#CHECK: trtr 4095(1,%r1), 0 # encoding: [0xd0,0x00,0x1f,0xff,0x00,0x00]
+#CHECK: trtr 4095(1,%r15), 0 # encoding: [0xd0,0x00,0xff,0xff,0x00,0x00]
+#CHECK: trtr 0(256,%r1), 0 # encoding: [0xd0,0xff,0x10,0x00,0x00,0x00]
+#CHECK: trtr 0(256,%r15), 0 # encoding: [0xd0,0xff,0xf0,0x00,0x00,0x00]
+
+ trtr 0(1), 0
+ trtr 0(1), 0(%r1)
+ trtr 0(1), 0(%r15)
+ trtr 0(1), 4095
+ trtr 0(1), 4095(%r1)
+ trtr 0(1), 4095(%r15)
+ trtr 0(1,%r1), 0
+ trtr 0(1,%r15), 0
+ trtr 4095(1,%r1), 0
+ trtr 4095(1,%r15), 0
+ trtr 0(256,%r1), 0
+ trtr 0(256,%r15), 0
+
+#CHECK: trtre %r0, %r0 # encoding: [0xb9,0xbd,0x00,0x00]
+#CHECK: trtre %r0, %r15 # encoding: [0xb9,0xbd,0x00,0x0f]
+#CHECK: trtre %r14, %r0 # encoding: [0xb9,0xbd,0x00,0xe0]
+#CHECK: trtre %r6, %r8 # encoding: [0xb9,0xbd,0x00,0x68]
+#CHECK: trtre %r4, %r13, 0 # encoding: [0xb9,0xbd,0x00,0x4d]
+#CHECK: trtre %r4, %r13, 15 # encoding: [0xb9,0xbd,0xf0,0x4d]
+
+ trtre %r0, %r0
+ trtre %r0, %r15
+ trtre %r14, %r0
+ trtre %r6, %r8
+ trtre %r4, %r13, 0
+ trtre %r4, %r13, 15
+
+#CHECK: trtt %r0, %r0 # encoding: [0xb9,0x90,0x00,0x00]
+#CHECK: trtt %r0, %r15 # encoding: [0xb9,0x90,0x00,0x0f]
+#CHECK: trtt %r14, %r0 # encoding: [0xb9,0x90,0x00,0xe0]
+#CHECK: trtt %r6, %r8 # encoding: [0xb9,0x90,0x00,0x68]
+#CHECK: trtt %r4, %r13, 0 # encoding: [0xb9,0x90,0x00,0x4d]
+#CHECK: trtt %r4, %r13, 15 # encoding: [0xb9,0x90,0xf0,0x4d]
+
+ trtt %r0, %r0
+ trtt %r0, %r15
+ trtt %r14, %r0
+ trtt %r6, %r8
+ trtt %r4, %r13, 0
+ trtt %r4, %r13, 15
+
#CHECK: ts 0 # encoding: [0x93,0x00,0x00,0x00]
#CHECK: ts 0(%r1) # encoding: [0x93,0x00,0x10,0x00]
#CHECK: ts 0(%r15) # encoding: [0x93,0x00,0xf0,0x00]
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