[llvm] r302643 - [SystemZ] Add missing memory/string instructions
Ulrich Weigand via llvm-commits
llvm-commits at lists.llvm.org
Wed May 10 05:40:16 PDT 2017
Author: uweigand
Date: Wed May 10 07:40:15 2017
New Revision: 302643
URL: http://llvm.org/viewvc/llvm-project?rev=302643&view=rev
Log:
[SystemZ] Add missing memory/string instructions
This adds a number of missing memory and string instructions
for assembler / disassembler use.
Modified:
llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td
llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ13.td
llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ196.td
llvm/trunk/lib/Target/SystemZ/SystemZScheduleZEC12.td
llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt
llvm/trunk/test/MC/SystemZ/insn-bad.s
llvm/trunk/test/MC/SystemZ/insn-good.s
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td?rev=302643&r1=302642&r2=302643&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td Wed May 10 07:40:15 2017
@@ -2590,6 +2590,26 @@ class SideEffectBinarySIL<string mnemoni
: InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
mnemonic#"\t$BD1, $I2", [(operator bdaddr12only:$BD1, imm:$I2)]>;
+class SideEffectBinarySSa<string mnemonic, bits<8> opcode>
+ : InstSSa<opcode, (outs), (ins bdladdr12onlylen8:$BDL1, bdaddr12only:$BD2),
+ mnemonic##"\t$BDL1, $BD2", []>;
+
+class SideEffectBinaryMemMemRR<string mnemonic, bits<8> opcode,
+ RegisterOperand cls1, RegisterOperand cls2>
+ : InstRR<opcode, (outs cls1:$R1, cls2:$R2), (ins cls1:$R1src, cls2:$R2src),
+ mnemonic#"\t$R1, $R2", []> {
+ let Constraints = "$R1 = $R1src, $R2 = $R2src";
+ let DisableEncoding = "$R1src, $R2src";
+}
+
+class SideEffectBinaryMemMemRRE<string mnemonic, bits<16> opcode,
+ RegisterOperand cls1, RegisterOperand cls2>
+ : InstRRE<opcode, (outs cls1:$R1, cls2:$R2), (ins cls1:$R1src, cls2:$R2src),
+ mnemonic#"\t$R1, $R2", []> {
+ let Constraints = "$R1 = $R1src, $R2 = $R2src";
+ let DisableEncoding = "$R1src, $R2src";
+}
+
class BinaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
RegisterOperand cls1, RegisterOperand cls2>
: InstRR<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
@@ -3376,6 +3396,24 @@ multiclass TernaryRSPair<string mnemonic
}
}
+class SideEffectTernaryMemMemRS<string mnemonic, bits<8> opcode,
+ RegisterOperand cls1, RegisterOperand cls2>
+ : InstRSa<opcode, (outs cls1:$R1, cls2:$R3),
+ (ins cls1:$R1src, cls2:$R3src, shift12only:$BD2),
+ mnemonic#"\t$R1, $R3, $BD2", []> {
+ let Constraints = "$R1 = $R1src, $R3 = $R3src";
+ let DisableEncoding = "$R1src, $R3src";
+}
+
+class SideEffectTernaryMemMemRSY<string mnemonic, bits<16> opcode,
+ RegisterOperand cls1, RegisterOperand cls2>
+ : InstRSYa<opcode, (outs cls1:$R1, cls2:$R3),
+ (ins cls1:$R1src, cls2:$R3src, shift20only:$BD2),
+ mnemonic#"\t$R1, $R3, $BD2", []> {
+ let Constraints = "$R1 = $R1src, $R3 = $R3src";
+ let DisableEncoding = "$R1src, $R3src";
+}
+
class TernaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
: InstRXF<opcode, (outs cls:$R1),
@@ -3981,9 +4019,7 @@ class AtomicLoadWBinaryImm<SDPatternOper
// another instruction to handle the excess.
multiclass MemorySS<string mnemonic, bits<8> opcode,
SDPatternOperator sequence, SDPatternOperator loop> {
- def "" : InstSSa<opcode, (outs), (ins bdladdr12onlylen8:$BDL1,
- bdaddr12only:$BD2),
- mnemonic##"\t$BDL1, $BD2", []>;
+ def "" : SideEffectBinarySSa<mnemonic, opcode>;
let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in {
def Sequence : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src,
imm64:$length),
@@ -4003,13 +4039,8 @@ multiclass MemorySS<string mnemonic, bit
// the full loop (the main instruction plus the branch on CC==3).
multiclass StringRRE<string mnemonic, bits<16> opcode,
SDPatternOperator operator> {
- def "" : InstRRE<opcode, (outs GR64:$R1, GR64:$R2),
- (ins GR64:$R1src, GR64:$R2src),
- mnemonic#"\t$R1, $R2", []> {
- let Uses = [R0L];
- let Constraints = "$R1 = $R1src, $R2 = $R2src";
- let DisableEncoding = "$R1src, $R2src";
- }
+ let Uses = [R0L] in
+ def "" : SideEffectBinaryMemMemRRE<mnemonic, opcode, GR64, GR64>;
let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in
def Loop : Pseudo<(outs GR64:$end),
(ins GR64:$start1, GR64:$start2, GR32:$char),
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td?rev=302643&r1=302642&r2=302643&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td Wed May 10 07:40:15 2017
@@ -464,6 +464,11 @@ def MVGHI : StoreSIL<"mvghi", 0xE548, st
// Memory-to-memory moves.
let mayLoad = 1, mayStore = 1 in
defm MVC : MemorySS<"mvc", 0xD2, z_mvc, z_mvc_loop>;
+let mayLoad = 1, mayStore = 1, Defs = [CC] in {
+ def MVCL : SideEffectBinaryMemMemRR<"mvcl", 0x0E, GR128, GR128>;
+ def MVCLE : SideEffectTernaryMemMemRS<"mvcle", 0xA8, GR128, GR128>;
+ def MVCLU : SideEffectTernaryMemMemRSY<"mvclu", 0xEB8E, GR128, GR128>;
+}
// String moves.
let mayLoad = 1, mayStore = 1, Defs = [CC] in
@@ -742,6 +747,10 @@ def STRVH : StoreRXY<"strvh", 0xE33F, z_
def STRV : StoreRXY<"strv", 0xE33E, z_strv, GR32, 4>;
def STRVG : StoreRXY<"strvg", 0xE32F, z_strvg, GR64, 8>;
+// Byte-swapping memory-to-memory moves.
+let mayLoad = 1, mayStore = 1 in
+ def MVCIN : SideEffectBinarySSa<"mvcin", 0xE8>;
+
//===----------------------------------------------------------------------===//
// Load address instructions
//===----------------------------------------------------------------------===//
@@ -1351,8 +1360,12 @@ let Defs = [CC], CCValues = 0xE, IsLogic
defm : ZXB<z_ucmp, GR64, CLGFR>;
// Memory-to-memory comparison.
-let mayLoad = 1, Defs = [CC] in
+let mayLoad = 1, Defs = [CC] in {
defm CLC : MemorySS<"clc", 0xD5, z_clc, z_clc_loop>;
+ def CLCL : SideEffectBinaryMemMemRR<"clcl", 0x0F, GR128, GR128>;
+ def CLCLE : SideEffectTernaryMemMemRS<"clcle", 0xA9, GR128, GR128>;
+ def CLCLU : SideEffectTernaryMemMemRSY<"clclu", 0xEB8F, GR128, GR128>;
+}
// String comparison.
let mayLoad = 1, Defs = [CC] in
@@ -1712,7 +1725,13 @@ let usesCustomInserter = 1 in {
// Search a block of memory for a character.
let mayLoad = 1, Defs = [CC] in
- defm SRST : StringRRE<"srst", 0xb25e, z_search_string>;
+ defm SRST : StringRRE<"srst", 0xB25E, z_search_string>;
+let mayLoad = 1, Defs = [CC], Uses = [R0L] in
+ def SRSTU : SideEffectBinaryMemMemRRE<"srstu", 0xB9BE, GR64, GR64>;
+
+// Compare until substring equal.
+let mayLoad = 1, Defs = [CC], Uses = [R0L, R1L] in
+ def CUSE : SideEffectBinaryMemMemRRE<"cuse", 0xB257, GR128, GR128>;
// Supervisor call.
let hasSideEffects = 1, isCall = 1, Defs = [CC] in
Modified: llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ13.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ13.td?rev=302643&r1=302642&r2=302643&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ13.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ13.td Wed May 10 07:40:15 2017
@@ -179,6 +179,7 @@ def : InstRW<[FXb, LSU, Lat5], (instrege
// Move character
def : InstRW<[FXb, LSU, LSU, LSU, Lat8, GroupAlone], (instregex "MVC$")>;
+def : InstRW<[LSU, Lat30, GroupAlone], (instregex "MVCL(E|U)?$")>;
// Pseudo -> reg move
def : InstRW<[FXa], (instregex "COPY(_TO_REGCLASS)?$")>;
@@ -288,6 +289,7 @@ def : InstRW<[LSU, LSU, FXb, FXb, FXb, L
def : InstRW<[FXa], (instregex "LRV(G)?R$")>;
def : InstRW<[FXa, LSU, Lat5], (instregex "LRV(G|H)?$")>;
def : InstRW<[FXb, LSU, Lat5], (instregex "STRV(G|H)?$")>;
+def : InstRW<[LSU, Lat30, GroupAlone], (instregex "MVCIN$")>;
//===----------------------------------------------------------------------===//
// Load address instructions
@@ -505,7 +507,7 @@ def : InstRW<[FXb, Lat2], (instregex "CG
// Compare logical character
def : InstRW<[FXb, LSU, LSU, Lat9, BeginGroup], (instregex "CLC$")>;
-
+def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CLCL(E|U)?$")>;
def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CLST$")>;
// Test under mask
@@ -640,6 +642,8 @@ def : InstRW<[FXa], (instregex "ZEXT128_
// String instructions
def : InstRW<[FXa, LSU, Lat30], (instregex "SRST$")>;
+def : InstRW<[LSU, Lat30], (instregex "SRSTU$")>;
+def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CUSE$")>;
// Move with key
def : InstRW<[FXa, FXa, FXb, LSU, Lat8, GroupAlone], (instregex "MVCK$")>;
Modified: llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ196.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ196.td?rev=302643&r1=302642&r2=302643&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ196.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ196.td Wed May 10 07:40:15 2017
@@ -152,6 +152,7 @@ def : InstRW<[FXU, LSU, Lat5], (instrege
// Move character
def : InstRW<[LSU, LSU, LSU, FXU, Lat8, GroupAlone], (instregex "MVC$")>;
+def : InstRW<[LSU, Lat30, GroupAlone], (instregex "MVCL(E|U)?$")>;
// Pseudo -> reg move
def : InstRW<[FXU], (instregex "COPY(_TO_REGCLASS)?$")>;
@@ -246,6 +247,7 @@ def : InstRW<[LSU, LSU, FXU, FXU, FXU, L
def : InstRW<[FXU], (instregex "LRV(G)?R$")>;
def : InstRW<[FXU, LSU, Lat5], (instregex "LRV(G|H)?$")>;
def : InstRW<[FXU, LSU, Lat5], (instregex "STRV(G|H)?$")>;
+def : InstRW<[LSU, Lat30, GroupAlone], (instregex "MVCIN$")>;
//===----------------------------------------------------------------------===//
// Load address instructions
@@ -465,7 +467,7 @@ def : InstRW<[FXU, FXU, Lat2, GroupAlone
// Compare logical character
def : InstRW<[LSU, LSU, FXU, Lat9, GroupAlone], (instregex "CLC$")>;
-
+def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CLCL(E|U)?$")>;
def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CLST$")>;
// Test under mask
@@ -571,6 +573,8 @@ def : InstRW<[FXU], (instregex "ZEXT128_
// String instructions
def : InstRW<[FXU, LSU, Lat30], (instregex "SRST$")>;
+def : InstRW<[LSU, Lat30], (instregex "SRSTU$")>;
+def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CUSE$")>;
// Move with key
def : InstRW<[LSU, Lat8, GroupAlone], (instregex "MVCK$")>;
Modified: llvm/trunk/lib/Target/SystemZ/SystemZScheduleZEC12.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZScheduleZEC12.td?rev=302643&r1=302642&r2=302643&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZScheduleZEC12.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZScheduleZEC12.td Wed May 10 07:40:15 2017
@@ -155,6 +155,7 @@ def : InstRW<[FXU, LSU, Lat5], (instrege
// Move character
def : InstRW<[LSU, LSU, LSU, FXU, Lat8, GroupAlone], (instregex "MVC$")>;
+def : InstRW<[LSU, Lat30, GroupAlone], (instregex "MVCL(E|U)?$")>;
// Pseudo -> reg move
def : InstRW<[FXU], (instregex "COPY(_TO_REGCLASS)?$")>;
@@ -256,6 +257,7 @@ def : InstRW<[LSU, LSU, FXU, FXU, FXU, L
def : InstRW<[FXU], (instregex "LRV(G)?R$")>;
def : InstRW<[FXU, LSU, Lat5], (instregex "LRV(G|H)?$")>;
def : InstRW<[FXU, LSU, Lat5], (instregex "STRV(G|H)?$")>;
+def : InstRW<[LSU, Lat30, GroupAlone], (instregex "MVCIN$")>;
//===----------------------------------------------------------------------===//
// Load address instructions
@@ -475,7 +477,7 @@ def : InstRW<[FXU, Lat2], (instregex "CG
// Compare logical character
def : InstRW<[FXU, LSU, LSU, Lat9, GroupAlone], (instregex "CLC$")>;
-
+def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CLCL(E|U)?$")>;
def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CLST$")>;
// Test under mask
@@ -609,6 +611,8 @@ def : InstRW<[FXU], (instregex "ZEXT128_
// String instructions
def : InstRW<[FXU, LSU, Lat30], (instregex "SRST$")>;
+def : InstRW<[LSU, Lat30], (instregex "SRSTU$")>;
+def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CUSE$")>;
// Move with key
def : InstRW<[LSU, Lat8, GroupAlone], (instregex "MVCK$")>;
Modified: llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt?rev=302643&r1=302642&r2=302643&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt (original)
+++ llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt Wed May 10 07:40:15 2017
@@ -2491,6 +2491,69 @@
# CHECK: clc 0(256,%r15), 0
0xd5 0xff 0xf0 0x00 0x00 0x00
+# CHECK: clcl %r0, %r8
+0x0f 0x08
+
+# CHECK: clcl %r0, %r14
+0x0f 0x0e
+
+# CHECK: clcl %r14, %r0
+0x0f 0xe0
+
+# CHECK: clcl %r14, %r8
+0x0f 0xe8
+
+# CHECK: clcle %r0, %r0, 0
+0xa9 0x00 0x00 0x00
+
+# CHECK: clcle %r0, %r14, 4095
+0xa9 0x0e 0x0f 0xff
+
+# CHECK: clcle %r0, %r0, 0(%r1)
+0xa9 0x00 0x10 0x00
+
+# CHECK: clcle %r0, %r0, 0(%r15)
+0xa9 0x00 0xf0 0x00
+
+# CHECK: clcle %r0, %r14, 4095(%r15)
+0xa9 0x0e 0xff 0xff
+
+# CHECK: clcle %r0, %r0, 4095(%r1)
+0xa9 0x00 0x1f 0xff
+
+# CHECK: clcle %r14, %r0, 0
+0xa9 0xe0 0x00 0x00
+
+# CHECK: clclu %r0, %r0, -524288
+0xeb 0x00 0x00 0x00 0x80 0x8f
+
+# CHECK: clclu %r0, %r0, -1
+0xeb 0x00 0x0f 0xff 0xff 0x8f
+
+# CHECK: clclu %r0, %r14, 0
+0xeb 0x0e 0x00 0x00 0x00 0x8f
+
+# CHECK: clclu %r0, %r14, 1
+0xeb 0x0e 0x00 0x01 0x00 0x8f
+
+# CHECK: clclu %r0, %r8, 524287
+0xeb 0x08 0x0f 0xff 0x7f 0x8f
+
+# CHECK: clclu %r0, %r8, 0(%r1)
+0xeb 0x08 0x10 0x00 0x00 0x8f
+
+# CHECK: clclu %r0, %r4, 0(%r15)
+0xeb 0x04 0xf0 0x00 0x00 0x8f
+
+# CHECK: clclu %r0, %r4, 524287(%r15)
+0xeb 0x04 0xff 0xff 0x7f 0x8f
+
+# CHECK: clclu %r0, %r0, 524287(%r1)
+0xeb 0x00 0x1f 0xff 0x7f 0x8f
+
+# CHECK: clclu %r14, %r0, 0
+0xeb 0xe0 0x00 0x00 0x00 0x8f
+
# CHECK: clfdbr %r0, 0, %f0, 1
0xb3 0x9d 0x01 0x00
@@ -3583,6 +3646,18 @@
# CHECK: csy %r15, %r0, 0
0xeb 0xf0 0x00 0x00 0x00 0x14
+# CHECK: cuse %r0, %r0
+0xb2 0x57 0x00 0x00
+
+# CHECK: cuse %r0, %r14
+0xb2 0x57 0x00 0x0e
+
+# CHECK: cuse %r14, %r0
+0xb2 0x57 0x00 0xe0
+
+# CHECK: cuse %r6, %r8
+0xb2 0x57 0x00 0x68
+
# CHECK: cxbr %f0, %f0
0xb3 0x49 0x00 0x00
@@ -7738,6 +7813,42 @@
# CHECK: mvc 0(256,%r15), 0
0xd2 0xff 0xf0 0x00 0x00 0x00
+# CHECK: mvcin 0(1), 0
+0xe8 0x00 0x00 0x00 0x00 0x00
+
+# CHECK: mvcin 0(1), 0(%r1)
+0xe8 0x00 0x00 0x00 0x10 0x00
+
+# CHECK: mvcin 0(1), 0(%r15)
+0xe8 0x00 0x00 0x00 0xf0 0x00
+
+# CHECK: mvcin 0(1), 4095
+0xe8 0x00 0x00 0x00 0x0f 0xff
+
+# CHECK: mvcin 0(1), 4095(%r1)
+0xe8 0x00 0x00 0x00 0x1f 0xff
+
+# CHECK: mvcin 0(1), 4095(%r15)
+0xe8 0x00 0x00 0x00 0xff 0xff
+
+# CHECK: mvcin 0(1,%r1), 0
+0xe8 0x00 0x10 0x00 0x00 0x00
+
+# CHECK: mvcin 0(1,%r15), 0
+0xe8 0x00 0xf0 0x00 0x00 0x00
+
+# CHECK: mvcin 4095(1,%r1), 0
+0xe8 0x00 0x1f 0xff 0x00 0x00
+
+# CHECK: mvcin 4095(1,%r15), 0
+0xe8 0x00 0xff 0xff 0x00 0x00
+
+# CHECK: mvcin 0(256,%r1), 0
+0xe8 0xff 0x10 0x00 0x00 0x00
+
+# CHECK: mvcin 0(256,%r15), 0
+0xe8 0xff 0xf0 0x00 0x00 0x00
+
# CHECK: mvck 0(%r0), 0, %r0
0xd9 0x00 0x00 0x00 0x00 0x00
@@ -7759,6 +7870,69 @@
# CHECK: mvck 4095(%r15,%r1), 0(%r15), %r2
0xd9 0xf2 0x1f 0xff 0xf0 0x00
+# CHECK: mvcl %r0, %r8
+0x0e 0x08
+
+# CHECK: mvcl %r0, %r14
+0x0e 0x0e
+
+# CHECK: mvcl %r14, %r0
+0x0e 0xe0
+
+# CHECK: mvcl %r14, %r8
+0x0e 0xe8
+
+# CHECK: mvcle %r0, %r0, 0
+0xa8 0x00 0x00 0x00
+
+# CHECK: mvcle %r0, %r14, 4095
+0xa8 0x0e 0x0f 0xff
+
+# CHECK: mvcle %r0, %r0, 0(%r1)
+0xa8 0x00 0x10 0x00
+
+# CHECK: mvcle %r0, %r0, 0(%r15)
+0xa8 0x00 0xf0 0x00
+
+# CHECK: mvcle %r0, %r14, 4095(%r15)
+0xa8 0x0e 0xff 0xff
+
+# CHECK: mvcle %r0, %r0, 4095(%r1)
+0xa8 0x00 0x1f 0xff
+
+# CHECK: mvcle %r14, %r0, 0
+0xa8 0xe0 0x00 0x00
+
+# CHECK: mvclu %r0, %r0, -524288
+0xeb 0x00 0x00 0x00 0x80 0x8e
+
+# CHECK: mvclu %r0, %r0, -1
+0xeb 0x00 0x0f 0xff 0xff 0x8e
+
+# CHECK: mvclu %r0, %r14, 0
+0xeb 0x0e 0x00 0x00 0x00 0x8e
+
+# CHECK: mvclu %r0, %r14, 1
+0xeb 0x0e 0x00 0x01 0x00 0x8e
+
+# CHECK: mvclu %r0, %r8, 524287
+0xeb 0x08 0x0f 0xff 0x7f 0x8e
+
+# CHECK: mvclu %r0, %r8, 0(%r1)
+0xeb 0x08 0x10 0x00 0x00 0x8e
+
+# CHECK: mvclu %r0, %r4, 0(%r15)
+0xeb 0x04 0xf0 0x00 0x00 0x8e
+
+# CHECK: mvclu %r0, %r4, 524287(%r15)
+0xeb 0x04 0xff 0xff 0x7f 0x8e
+
+# CHECK: mvclu %r0, %r0, 524287(%r1)
+0xeb 0x00 0x1f 0xff 0x7f 0x8e
+
+# CHECK: mvclu %r14, %r0, 0
+0xeb 0xe0 0x00 0x00 0x00 0x8e
+
# CHECK: mvghi 0, 0
0xe5 0x48 0x00 0x00 0x00 0x00
@@ -9898,6 +10072,18 @@
# CHECK: srst %r7, %r8
0xb2 0x5e 0x00 0x78
+# CHECK: srstu %r0, %r0
+0xb9 0xbe 0x00 0x00
+
+# CHECK: srstu %r0, %r15
+0xb9 0xbe 0x00 0x0f
+
+# CHECK: srstu %r15, %r0
+0xb9 0xbe 0x00 0xf0
+
+# CHECK: srstu %r7, %r8
+0xb9 0xbe 0x00 0x78
+
# CHECK: st %r0, 0
0x50 0x00 0x00 0x00
Modified: llvm/trunk/test/MC/SystemZ/insn-bad.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/SystemZ/insn-bad.s?rev=302643&r1=302642&r2=302643&view=diff
==============================================================================
--- llvm/trunk/test/MC/SystemZ/insn-bad.s (original)
+++ llvm/trunk/test/MC/SystemZ/insn-bad.s Wed May 10 07:40:15 2017
@@ -1081,6 +1081,42 @@
clc 0(1,%r2), 0(%r1,%r2)
clc 0(-), 0
+#CHECK: error: invalid register pair
+#CHECK: clcl %r1, %r0
+#CHECK: error: invalid register pair
+#CHECK: clcl %r0, %r1
+
+ clcl %r1, %r0
+ clcl %r0, %r1
+
+#CHECK: error: invalid register pair
+#CHECK: clcle %r1, %r0
+#CHECK: error: invalid register pair
+#CHECK: clcle %r0, %r1
+#CHECK: error: invalid operand
+#CHECK: clcle %r0, %r0, -1
+#CHECK: error: invalid operand
+#CHECK: clcle %r0, %r0, 4096
+
+ clcle %r1, %r0, 0
+ clcle %r0, %r1, 0
+ clcle %r0, %r0, -1
+ clcle %r0, %r0, 4096
+
+#CHECK: error: invalid register pair
+#CHECK: clclu %r1, %r0
+#CHECK: error: invalid register pair
+#CHECK: clclu %r0, %r1
+#CHECK: error: invalid operand
+#CHECK: clclu %r0, %r0, -524289
+#CHECK: error: invalid operand
+#CHECK: clclu %r0, %r0, 524288
+
+ clclu %r1, %r0, 0
+ clclu %r0, %r1, 0
+ clclu %r0, %r0, -524289
+ clclu %r0, %r0, 524288
+
#CHECK: error: instruction requires: fp-extension
#CHECK: clfdbr %r0, 0, %f0, 0
@@ -1551,6 +1587,14 @@
csy %r0, %r0, 0(%r1,%r2)
#CHECK: error: invalid register pair
+#CHECK: cuse %r1, %r0
+#CHECK: error: invalid register pair
+#CHECK: cuse %r0, %r1
+
+ cuse %r1, %r0
+ cuse %r0, %r1
+
+#CHECK: error: invalid register pair
#CHECK: cxbr %f0, %f2
#CHECK: error: invalid register pair
#CHECK: cxbr %f2, %f0
@@ -2745,6 +2789,50 @@
mvc 0(1,%r2), 0(%r1,%r2)
mvc 0(-), 0
+#CHECK: error: missing length in address
+#CHECK: mvcin 0, 0
+#CHECK: error: missing length in address
+#CHECK: mvcin 0(%r1), 0(%r1)
+#CHECK: error: invalid use of length addressing
+#CHECK: mvcin 0(1,%r1), 0(2,%r1)
+#CHECK: error: invalid operand
+#CHECK: mvcin 0(0,%r1), 0(%r1)
+#CHECK: error: invalid operand
+#CHECK: mvcin 0(257,%r1), 0(%r1)
+#CHECK: error: invalid operand
+#CHECK: mvcin -1(1,%r1), 0(%r1)
+#CHECK: error: invalid operand
+#CHECK: mvcin 4096(1,%r1), 0(%r1)
+#CHECK: error: invalid operand
+#CHECK: mvcin 0(1,%r1), -1(%r1)
+#CHECK: error: invalid operand
+#CHECK: mvcin 0(1,%r1), 4096(%r1)
+#CHECK: error: %r0 used in an address
+#CHECK: mvcin 0(1,%r0), 0(%r1)
+#CHECK: error: %r0 used in an address
+#CHECK: mvcin 0(1,%r1), 0(%r0)
+#CHECK: error: invalid use of indexed addressing
+#CHECK: mvcin 0(%r1,%r2), 0(%r1)
+#CHECK: error: invalid use of indexed addressing
+#CHECK: mvcin 0(1,%r2), 0(%r1,%r2)
+#CHECK: error: unknown token in expression
+#CHECK: mvcin 0(-), 0
+
+ mvcin 0, 0
+ mvcin 0(%r1), 0(%r1)
+ mvcin 0(1,%r1), 0(2,%r1)
+ mvcin 0(0,%r1), 0(%r1)
+ mvcin 0(257,%r1), 0(%r1)
+ mvcin -1(1,%r1), 0(%r1)
+ mvcin 4096(1,%r1), 0(%r1)
+ mvcin 0(1,%r1), -1(%r1)
+ mvcin 0(1,%r1), 4096(%r1)
+ mvcin 0(1,%r0), 0(%r1)
+ mvcin 0(1,%r1), 0(%r0)
+ mvcin 0(%r1,%r2), 0(%r1)
+ mvcin 0(1,%r2), 0(%r1,%r2)
+ mvcin 0(-), 0
+
#CHECK: error: invalid use of length addressing
#CHECK: mvck 0(%r1,%r1), 0(2,%r1), %r3
#CHECK: error: invalid operand
@@ -2774,6 +2862,42 @@
mvck 0(%r1,%r2), 0(%r1,%r2), %r3
mvck 0(-), 0, %r3
+#CHECK: error: invalid register pair
+#CHECK: mvcl %r1, %r0
+#CHECK: error: invalid register pair
+#CHECK: mvcl %r0, %r1
+
+ mvcl %r1, %r0
+ mvcl %r0, %r1
+
+#CHECK: error: invalid register pair
+#CHECK: mvcle %r1, %r0
+#CHECK: error: invalid register pair
+#CHECK: mvcle %r0, %r1
+#CHECK: error: invalid operand
+#CHECK: mvcle %r0, %r0, -1
+#CHECK: error: invalid operand
+#CHECK: mvcle %r0, %r0, 4096
+
+ mvcle %r1, %r0, 0
+ mvcle %r0, %r1, 0
+ mvcle %r0, %r0, -1
+ mvcle %r0, %r0, 4096
+
+#CHECK: error: invalid register pair
+#CHECK: mvclu %r1, %r0
+#CHECK: error: invalid register pair
+#CHECK: mvclu %r0, %r1
+#CHECK: error: invalid operand
+#CHECK: mvclu %r0, %r0, -524289
+#CHECK: error: invalid operand
+#CHECK: mvclu %r0, %r0, 524288
+
+ mvclu %r1, %r0, 0
+ mvclu %r0, %r1, 0
+ mvclu %r0, %r0, -524289
+ mvclu %r0, %r0, 524288
+
#CHECK: error: invalid operand
#CHECK: mvghi -1, 0
#CHECK: error: invalid operand
Modified: llvm/trunk/test/MC/SystemZ/insn-good.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/SystemZ/insn-good.s?rev=302643&r1=302642&r2=302643&view=diff
==============================================================================
--- llvm/trunk/test/MC/SystemZ/insn-good.s (original)
+++ llvm/trunk/test/MC/SystemZ/insn-good.s Wed May 10 07:40:15 2017
@@ -3477,6 +3477,54 @@
clc 0(256,%r1), 0
clc 0(256,%r15), 0
+#CHECK: clcl %r0, %r8 # encoding: [0x0f,0x08]
+#CHECK: clcl %r0, %r14 # encoding: [0x0f,0x0e]
+#CHECK: clcl %r14, %r0 # encoding: [0x0f,0xe0]
+#CHECK: clcl %r14, %r8 # encoding: [0x0f,0xe8]
+
+ clcl %r0, %r8
+ clcl %r0, %r14
+ clcl %r14, %r0
+ clcl %r14, %r8
+
+#CHECK: clcle %r0, %r0, 0 # encoding: [0xa9,0x00,0x00,0x00]
+#CHECK: clcle %r0, %r14, 4095 # encoding: [0xa9,0x0e,0x0f,0xff]
+#CHECK: clcle %r0, %r0, 0(%r1) # encoding: [0xa9,0x00,0x10,0x00]
+#CHECK: clcle %r0, %r0, 0(%r15) # encoding: [0xa9,0x00,0xf0,0x00]
+#CHECK: clcle %r14, %r14, 4095(%r1) # encoding: [0xa9,0xee,0x1f,0xff]
+#CHECK: clcle %r0, %r0, 4095(%r15) # encoding: [0xa9,0x00,0xff,0xff]
+#CHECK: clcle %r14, %r0, 0 # encoding: [0xa9,0xe0,0x00,0x00]
+
+ clcle %r0, %r0, 0
+ clcle %r0, %r14, 4095
+ clcle %r0, %r0, 0(%r1)
+ clcle %r0, %r0, 0(%r15)
+ clcle %r14, %r14, 4095(%r1)
+ clcle %r0, %r0, 4095(%r15)
+ clcle %r14, %r0, 0
+
+#CHECK: clclu %r0, %r0, -524288 # encoding: [0xeb,0x00,0x00,0x00,0x80,0x8f]
+#CHECK: clclu %r0, %r0, -1 # encoding: [0xeb,0x00,0x0f,0xff,0xff,0x8f]
+#CHECK: clclu %r0, %r14, 0 # encoding: [0xeb,0x0e,0x00,0x00,0x00,0x8f]
+#CHECK: clclu %r0, %r14, 1 # encoding: [0xeb,0x0e,0x00,0x01,0x00,0x8f]
+#CHECK: clclu %r0, %r8, 524287 # encoding: [0xeb,0x08,0x0f,0xff,0x7f,0x8f]
+#CHECK: clclu %r0, %r8, 0(%r1) # encoding: [0xeb,0x08,0x10,0x00,0x00,0x8f]
+#CHECK: clclu %r0, %r4, 0(%r15) # encoding: [0xeb,0x04,0xf0,0x00,0x00,0x8f]
+#CHECK: clclu %r0, %r4, 524287(%r15) # encoding: [0xeb,0x04,0xff,0xff,0x7f,0x8f]
+#CHECK: clclu %r0, %r0, 524287(%r1) # encoding: [0xeb,0x00,0x1f,0xff,0x7f,0x8f]
+#CHECK: clclu %r14, %r0, 0 # encoding: [0xeb,0xe0,0x00,0x00,0x00,0x8f]
+
+ clclu %r0, %r0, -524288
+ clclu %r0, %r0, -1
+ clclu %r0, %r14, 0
+ clclu %r0, %r14, 1
+ clclu %r0, %r8, 524287
+ clclu %r0, %r8, 0(%r1)
+ clclu %r0, %r4, 0(%r15)
+ clclu %r0, %r4, 524287(%r15)
+ clclu %r0, %r0, 524287(%r1)
+ clclu %r14, %r0, 0
+
#CHECK: clfhsi 0, 0 # encoding: [0xe5,0x5d,0x00,0x00,0x00,0x00]
#CHECK: clfhsi 4095, 0 # encoding: [0xe5,0x5d,0x0f,0xff,0x00,0x00]
#CHECK: clfhsi 0, 65535 # encoding: [0xe5,0x5d,0x00,0x00,0xff,0xff]
@@ -5661,6 +5709,16 @@
csy %r0, %r15, 0
csy %r15, %r0, 0
+#CHECK: cuse %r0, %r8 # encoding: [0xb2,0x57,0x00,0x08]
+#CHECK: cuse %r0, %r14 # encoding: [0xb2,0x57,0x00,0x0e]
+#CHECK: cuse %r14, %r0 # encoding: [0xb2,0x57,0x00,0xe0]
+#CHECK: cuse %r14, %r8 # encoding: [0xb2,0x57,0x00,0xe8]
+
+ cuse %r0, %r8
+ cuse %r0, %r14
+ cuse %r14, %r0
+ cuse %r14, %r8
+
#CHECK: cxbr %f0, %f0 # encoding: [0xb3,0x49,0x00,0x00]
#CHECK: cxbr %f0, %f13 # encoding: [0xb3,0x49,0x00,0x0d]
#CHECK: cxbr %f8, %f8 # encoding: [0xb3,0x49,0x00,0x88]
@@ -8434,6 +8492,32 @@
mvc 0(256,%r1), 0
mvc 0(256,%r15), 0
+#CHECK: mvcin 0(1), 0 # encoding: [0xe8,0x00,0x00,0x00,0x00,0x00]
+#CHECK: mvcin 0(1), 0(%r1) # encoding: [0xe8,0x00,0x00,0x00,0x10,0x00]
+#CHECK: mvcin 0(1), 0(%r15) # encoding: [0xe8,0x00,0x00,0x00,0xf0,0x00]
+#CHECK: mvcin 0(1), 4095 # encoding: [0xe8,0x00,0x00,0x00,0x0f,0xff]
+#CHECK: mvcin 0(1), 4095(%r1) # encoding: [0xe8,0x00,0x00,0x00,0x1f,0xff]
+#CHECK: mvcin 0(1), 4095(%r15) # encoding: [0xe8,0x00,0x00,0x00,0xff,0xff]
+#CHECK: mvcin 0(1,%r1), 0 # encoding: [0xe8,0x00,0x10,0x00,0x00,0x00]
+#CHECK: mvcin 0(1,%r15), 0 # encoding: [0xe8,0x00,0xf0,0x00,0x00,0x00]
+#CHECK: mvcin 4095(1,%r1), 0 # encoding: [0xe8,0x00,0x1f,0xff,0x00,0x00]
+#CHECK: mvcin 4095(1,%r15), 0 # encoding: [0xe8,0x00,0xff,0xff,0x00,0x00]
+#CHECK: mvcin 0(256,%r1), 0 # encoding: [0xe8,0xff,0x10,0x00,0x00,0x00]
+#CHECK: mvcin 0(256,%r15), 0 # encoding: [0xe8,0xff,0xf0,0x00,0x00,0x00]
+
+ mvcin 0(1), 0
+ mvcin 0(1), 0(%r1)
+ mvcin 0(1), 0(%r15)
+ mvcin 0(1), 4095
+ mvcin 0(1), 4095(%r1)
+ mvcin 0(1), 4095(%r15)
+ mvcin 0(1,%r1), 0
+ mvcin 0(1,%r15), 0
+ mvcin 4095(1,%r1), 0
+ mvcin 4095(1,%r15), 0
+ mvcin 0(256,%r1), 0
+ mvcin 0(256,%r15), 0
+
#CHECK: mvck 0(%r0), 0, %r3 # encoding: [0xd9,0x03,0x00,0x00,0x00,0x00]
#CHECK: mvck 0(%r1), 0, %r3 # encoding: [0xd9,0x13,0x00,0x00,0x00,0x00]
#CHECK: mvck 0(%r1), 0(%r1), %r3 # encoding: [0xd9,0x13,0x00,0x00,0x10,0x00]
@@ -8462,6 +8546,54 @@
mvck 0(%r2,%r1), 0, %r3
mvck 0(%r2,%r15), 0, %r3
+#CHECK: mvcl %r0, %r8 # encoding: [0x0e,0x08]
+#CHECK: mvcl %r0, %r14 # encoding: [0x0e,0x0e]
+#CHECK: mvcl %r14, %r0 # encoding: [0x0e,0xe0]
+#CHECK: mvcl %r14, %r8 # encoding: [0x0e,0xe8]
+
+ mvcl %r0, %r8
+ mvcl %r0, %r14
+ mvcl %r14, %r0
+ mvcl %r14, %r8
+
+#CHECK: mvcle %r0, %r0, 0 # encoding: [0xa8,0x00,0x00,0x00]
+#CHECK: mvcle %r0, %r14, 4095 # encoding: [0xa8,0x0e,0x0f,0xff]
+#CHECK: mvcle %r0, %r0, 0(%r1) # encoding: [0xa8,0x00,0x10,0x00]
+#CHECK: mvcle %r0, %r0, 0(%r15) # encoding: [0xa8,0x00,0xf0,0x00]
+#CHECK: mvcle %r14, %r14, 4095(%r1) # encoding: [0xa8,0xee,0x1f,0xff]
+#CHECK: mvcle %r0, %r0, 4095(%r15) # encoding: [0xa8,0x00,0xff,0xff]
+#CHECK: mvcle %r14, %r0, 0 # encoding: [0xa8,0xe0,0x00,0x00]
+
+ mvcle %r0, %r0, 0
+ mvcle %r0, %r14, 4095
+ mvcle %r0, %r0, 0(%r1)
+ mvcle %r0, %r0, 0(%r15)
+ mvcle %r14, %r14, 4095(%r1)
+ mvcle %r0, %r0, 4095(%r15)
+ mvcle %r14, %r0, 0
+
+#CHECK: mvclu %r0, %r0, -524288 # encoding: [0xeb,0x00,0x00,0x00,0x80,0x8e]
+#CHECK: mvclu %r0, %r0, -1 # encoding: [0xeb,0x00,0x0f,0xff,0xff,0x8e]
+#CHECK: mvclu %r0, %r14, 0 # encoding: [0xeb,0x0e,0x00,0x00,0x00,0x8e]
+#CHECK: mvclu %r0, %r14, 1 # encoding: [0xeb,0x0e,0x00,0x01,0x00,0x8e]
+#CHECK: mvclu %r0, %r8, 524287 # encoding: [0xeb,0x08,0x0f,0xff,0x7f,0x8e]
+#CHECK: mvclu %r0, %r8, 0(%r1) # encoding: [0xeb,0x08,0x10,0x00,0x00,0x8e]
+#CHECK: mvclu %r0, %r4, 0(%r15) # encoding: [0xeb,0x04,0xf0,0x00,0x00,0x8e]
+#CHECK: mvclu %r0, %r4, 524287(%r15) # encoding: [0xeb,0x04,0xff,0xff,0x7f,0x8e]
+#CHECK: mvclu %r0, %r0, 524287(%r1) # encoding: [0xeb,0x00,0x1f,0xff,0x7f,0x8e]
+#CHECK: mvclu %r14, %r0, 0 # encoding: [0xeb,0xe0,0x00,0x00,0x00,0x8e]
+
+ mvclu %r0, %r0, -524288
+ mvclu %r0, %r0, -1
+ mvclu %r0, %r14, 0
+ mvclu %r0, %r14, 1
+ mvclu %r0, %r8, 524287
+ mvclu %r0, %r8, 0(%r1)
+ mvclu %r0, %r4, 0(%r15)
+ mvclu %r0, %r4, 524287(%r15)
+ mvclu %r0, %r0, 524287(%r1)
+ mvclu %r14, %r0, 0
+
#CHECK: mvghi 0, 0 # encoding: [0xe5,0x48,0x00,0x00,0x00,0x00]
#CHECK: mvghi 4095, 0 # encoding: [0xe5,0x48,0x0f,0xff,0x00,0x00]
#CHECK: mvghi 0, -32768 # encoding: [0xe5,0x48,0x00,0x00,0x80,0x00]
@@ -9882,6 +10014,16 @@
srst %r15,%r0
srst %r7,%r8
+#CHECK: srstu %r0, %r0 # encoding: [0xb9,0xbe,0x00,0x00]
+#CHECK: srstu %r0, %r15 # encoding: [0xb9,0xbe,0x00,0x0f]
+#CHECK: srstu %r15, %r0 # encoding: [0xb9,0xbe,0x00,0xf0]
+#CHECK: srstu %r7, %r8 # encoding: [0xb9,0xbe,0x00,0x78]
+
+ srstu %r0,%r0
+ srstu %r0,%r15
+ srstu %r15,%r0
+ srstu %r7,%r8
+
#CHECK: st %r0, 0 # encoding: [0x50,0x00,0x00,0x00]
#CHECK: st %r0, 4095 # encoding: [0x50,0x00,0x0f,0xff]
#CHECK: st %r0, 0(%r1) # encoding: [0x50,0x00,0x10,0x00]
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