[PATCH] D32869: [globalisel][tablegen] Require that all registers between instructions of a match are virtual.

[Daniel Sanders via Phabricator via llvm-commits]

dsanders created this revision.
Herald added a subscriber: igorb.

Without this, it's possible to encounter multiple defs for a register.

This is triggered by the current version of https://reviews.llvm.org/D32868 when applied to trunk.


https://reviews.llvm.org/D32869

Files:
  test/TableGen/GlobalISelEmitter.td
  utils/TableGen/GlobalISelEmitter.cpp


Index: utils/TableGen/GlobalISelEmitter.cpp
===================================================================
--- utils/TableGen/GlobalISelEmitter.cpp
+++ utils/TableGen/GlobalISelEmitter.cpp
@@ -776,6 +776,8 @@
   void emitCxxCaptureStmts(raw_ostream &OS, RuleMatcher &Rule,
                            StringRef OperandExpr) const override {
     OS << "if (!" << OperandExpr + ".isReg())\n"
+       << "  return false;\n"
+       << "if (TRI.isPhysicalRegister(" << OperandExpr + ".getReg()))\n"
        << "  return false;\n";
     std::string InsnVarName = Rule.defineInsnVar(
         OS, *InsnMatcher,
Index: test/TableGen/GlobalISelEmitter.td
===================================================================
--- test/TableGen/GlobalISelEmitter.td
+++ test/TableGen/GlobalISelEmitter.td
@@ -138,6 +138,8 @@
 // CHECK-NEXT:      return false;
 // CHECK-NEXT:    if (!MI0->getOperand(1).isReg())
 // CHECK-NEXT:      return false;
+// CHECK-NEXT:    if (TRI.isPhysicalRegister(MI0->getOperand(1).getReg()))
+// CHECK-NEXT:      return false;
 // CHECK-NEXT:    MachineInstr *MI1 = MRI.getVRegDef(MI0->getOperand(1).getReg());
 // CHECK-NEXT:    if (!MI1 || MI1->getNumOperands() < 3)
 // CHECK-NEXT:      return false;
@@ -180,6 +182,8 @@
 // CHECK-NEXT:      return false;
 // CHECK-NEXT:    if (!MI0->getOperand(2).isReg())
 // CHECK-NEXT:      return false;
+// CHECK-NEXT:    if (TRI.isPhysicalRegister(MI0->getOperand(2).getReg()))
+// CHECK-NEXT:      return false;
 // CHECK-NEXT:    MachineInstr *MI1 = MRI.getVRegDef(MI0->getOperand(2).getReg());
 // CHECK-NEXT:    if (!MI1 || MI1->getNumOperands() < 3)
 // CHECK-NEXT:      return false;


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D32869.97841.patch
Type: text/x-patch
Size: 1659 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20170504/556f9b60/attachment.bin>